Flip chip for AMD K6 microprocessor

Abstract

Flip-chip technology in the form of Controlled Collapse Connection (C4) was adopted for the AMD K6 microprocessor. The need arose from the pad limitations of wire-bond technology. The necessity of more pads for connectivity resulted in growth of die size. This would have impacted the net die per wafer and, therefore, the capacity of the wafer fabrication facilities. In addition, flip-chip technology afforded increased electrical performance. The paper describes the various materials/processes that were developed and qualified for manufacturing. The paper presents improvement to various traditional processes of flux application, flux cleaning, and underfill. The criterion used for the material and process development is described. In addition, reliability data are presented for two assembly sites, one in the US and the other in Malaysia. The data includes accelerated thermal cycles at two different conditions, and various underfill materials and cleaning methods. Also presented are the improvement to solder joint reliability due to use of underfill. In this particular application, it turned out to be at least 50X. The Malaysian facility is the first outside the United States to practice flip-chip technology in high-volume manufacturing for microprocessor application. This presented significant challenges in developing both equipment and support infrastructure. The paper concludes with a typical line layout of a high volume manufacturing line.