1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献

Dielectric constant and loss tangent measurement using a stripline fixture 介电常数和损耗正切测量使用带状线夹具

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-11-01 DOI: 10.1109/ECTC.1998.678848

Heping Yue, K. Virga, J. Prince

引用次数: 48

Use of compliant adhesives in the large area processing of MCM-D substrates 在MCM-D基材的大面积加工中使用柔性粘合剂

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-10-01 DOI: 10.1109/ECTC.1998.678814

S. Sitaraman, V. Sundararaman, S. Manjula, C. Wong, J. Wu, R. Pike

引用次数: 2

High density organic flip chip package substrate technology 高密度有机倒装晶片封装基板技术

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678850

W. G. Petefish, D.B. Noddin, David A. Hanson, R. Gorrell, M. F. Syvester

{"title":"High density organic flip chip package substrate technology","authors":"W. G. Petefish, D.B. Noddin, David A. Hanson, R. Gorrell, M. F. Syvester","doi":"10.1109/ECTC.1998.678850","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678850","url":null,"abstract":"High performance logic ICs are rapidly migrating from peripheral bonded package configurations to area array, flip chip configurations. Total die I/O is exploding from <800 pins to more than 3500 pins with little abatement in the rate of increase in total silicon area. Traditional flip chip package substrate technologies, such as co-fired ceramic, are not able to adequately support this growing industry trend due to inherent limitations in thermal cycling reliability of the level 2 interface, density, electrical performance, and cost of use. A new, cost effective, organic flip chip package substrate technology has been developed, prototyped, qualified, and is being ramped into production. This laminated technology uses a nonwoven polytetrafluoroethylene (PTFE) composite dielectric combined with a fabrication technology that has produced the highest density organic substrates yet disclosed. The technology has been used to fabricate packages for die up to 18.5 mm by 18.5 mm with more than 3800 total I/O. Body sizes of up to 45 mm have been fabricated. In this paper, we will discuss the materials of construction, process technology, reliability characterization, thermo-mechanical characterization, and electrical performance of various cross-sections using this new technology.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Nonlinear mechanical modeling of electrical connectors using simple numerical methods and secant modulus data 电连接器的非线性力学建模使用简单的数值方法和割线模量数据

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678664

J. L. Johnson

引用次数: 0

Hermetic-equivalent packaging of GPS MCM-L modules for high reliability avionics applications 用于高可靠性航空电子应用的GPS MCM-L模块的密封等效封装

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678813

J. Hagge, R. Camilletti

引用次数: 5

Theoretical and experimental approach for model extraction of multiconductor interconnects with multiple meshed planes on an APCB APCB多网格多导体互连模型提取的理论与实验方法

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678845

Y. Li, D. Figueroa, S. Zhong, L. Nguyen, T. Nguyen, L. Polka, J. Liao

{"title":"Theoretical and experimental approach for model extraction of multiconductor interconnects with multiple meshed planes on an APCB","authors":"Y. Li, D. Figueroa, S. Zhong, L. Nguyen, T. Nguyen, L. Polka, J. Liao","doi":"10.1109/ECTC.1998.678845","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678845","url":null,"abstract":"Multiple meshed power and ground planes are quite common in today's advanced PCB's (APCB's). The presence of meshed planes complicates the electrical modeling of interconnects in close proximity to these planes. In order to accurately model multiconductor interconnects near meshed planes, a set of test coupons was characterized. The multiconductor interconnects were modeled as cascaded lossy transmission lines. The interconnect models were validated by performing time- and frequency-domain simulations to match TDR and S-parameter measurements. The validation results from both the time and frequency domains show good agreement between the measured and simulated data. Using the interconnect model developed from the characterization results of the first set of test coupons, crosstalk models were built for multiconductor interconnects with meshed planes. To validate the crosstalk models, a second set of test coupons was analyzed. The crosstalk at both ends of each structure was measured. The measured results were compared with results from simulations. Reasonable agreement was seen between measured and simulated results and the discrepancy is being investigated further.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129477937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Formation of electrical contact through an Alodine coating 通过Alodine涂层形成电接触

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678666

A. Wehr, H. Hardee, N. Aukland, D. Klavens

引用次数: 0

Resolution and signal loss in acoustic microscopy of encapsulated IC packages 封装IC封装的声学显微镜分辨率和信号损失

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678825

S. Canumalla, M.G. Oravecz, L. W. Kessler

引用次数: 6

Optically interconnected integrated circuits to solve the CMOS interconnect bottleneck 光互联集成电路解决CMOS互连瓶颈

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678831

B. Dhoedt, R. Baets, P. van Daele, P. Heremans, J. V. Van Campenhout, J. Hall, R. Michalzik, A. Schmid, H. Thienpont, R. Vounckx, A. Neyer, D. O’brien, J. Van Koetsem

{"title":"Optically interconnected integrated circuits to solve the CMOS interconnect bottleneck","authors":"B. Dhoedt, R. Baets, P. van Daele, P. Heremans, J. V. Van Campenhout, J. Hall, R. Michalzik, A. Schmid, H. Thienpont, R. Vounckx, A. Neyer, D. O’brien, J. Van Koetsem","doi":"10.1109/ECTC.1998.678831","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678831","url":null,"abstract":"The performance of future generation data processing systems will be set by interconnect limitations rather than by IC performance. The main reason for this expected I/O-bottleneck is the projected increase in CMOS IC-complexity, in terms of chip size, number of I/O pads and clock frequency. Problems inherently associated with closely packed electrical interconnections (such as cross-talk, signal distortion EMI) will lead to bandwidth limitations, in turn resulting in a mismatch between silicon processing capabilities and interconnect performance. Optical I/O over the entire chip area is pursued as a solution to these interconnection problems in the European Community funded ESPRIT project OIIC (\"Optically Interconnected Integrated Circuits\"). In this approach, data transfer from the whole chip area is facilitated through two dimensional arrays (array pitch: 250 /spl mu/m) of optical channels, consisting of opto-electronic components flip-chip mounted on CMOS circuitry and aligned to passive optical pathways. Data rate objectives are 0.5-1 Gb/s per channel. As a principal choice in this project, a 2D array of small diameter (125 /spl mu/m) Plastic Optical Fibres is used as a flexible transmission medium. The large numerical aperture of this fibre (typically NA=0.5) and its flexibility allow for compact assembly (and hence low head room modules) and relatively coarse alignment.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123143088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Advanced ATM switching system hardware technology using MCM-D, stacking RAM microprocessor module 先进的ATM交换系统硬件技术采用MCM-D、堆叠RAM微处理器模块

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678812

N. Yamanaka, T. Kawamura, K. Kaizu, A. Harada

引用次数: 3