{"title":"In package micro-aligner for fiber-optic packaging","authors":"J. Haake, M. Beranek","doi":"10.1109/ECTC.1998.678934","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678934","url":null,"abstract":"We describe and demonstrate a 3-axis MEMS active fiber-optic micro-aligner, which will enable in-package alignment of fiber-optic and micro-optic components. The micro-aligner is a wafer level fabricated device, based on an integration of silicon micromachining and LIGA technology. The electrically controllable actuators demonstrate the high force and displacement necessary to overcome fiber-optic bending stiffness, counterforce springs, friction, and wirebonds, to perform active alignment of an optical fiber inside an optoelectronic package housing. We have demonstrated movement of >30 microns in all three axes in an in-package configuration. The first prototype devices are currently small enough (4/spl times/4/spl times/0.5 mm/sup 3/) to fit into a standard optoelectronic package. In the future we expect that micro-aligner devices with the same forces and displacements can be made smaller than 1/spl times/1/spl times/0.5 mm/sup 3/ thus allowing for multiple singlemode fiber-optic attachments inside standard optoelectronic package housings.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Caers, R. Oesterholt, R. Bressers, T. Mouthaan, J. F. Verweij
{"title":"Reliability of flip chip on board. First order model for the effect on contact integrity of moisture penetration in the underfill","authors":"J. Caers, R. Oesterholt, R. Bressers, T. Mouthaan, J. F. Verweij","doi":"10.1109/ECTC.1998.678809","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678809","url":null,"abstract":"In evaluating the reliability of flip chip on board with solder bumps, only a little is known about moisture-induced failure mechanisms at interconnection level. In order to accommodate the difference in coefficient of thermal expansion of the silicon die and the printed board in a flip chip geometry, an epoxy underfill is commonly applied. This underfill increases the resistance to cyclic temperature loads, but the material is susceptible to moisture ingress. Failure analysis of flip chips from an 85/spl deg/C/85%RH test has shown that swelling of the underfill caused by moisture take up and the resulting hygro-stress is a major driving force for failures at interconnection level. To capture this failure mechanism, a new first order, one dimensional diffusion model for moisture is used. Moisture absorption properties of underfills are experimentally determined by gravimetric vapour sorption experiments at 85/spl deg/C/85%RH. The temperature dependencies of these properties are estimated based on data of similar epoxy moulding compounds. Taking a critical hygro-stress level as failure criterion, an analytical transform is proposed, and an acceleration factor defined. A design rule for accelerated humidity testing is formulated. The acceleration transform is used to plot iso failure-free time diagrams for two flip chip underfills. These diagrams enable predicting of a failure-free time during service life under a variety of temperature and humidity conditions.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124728052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Hwang, Sang-Hwan Lee, G. Joo, Min-Kyu Song, K. Pyun
{"title":"Relationship between initial thermal characteristics and lifetime projection of semiconductor laser diodes","authors":"N. Hwang, Sang-Hwan Lee, G. Joo, Min-Kyu Song, K. Pyun","doi":"10.1109/ECTC.1998.678930","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678930","url":null,"abstract":"A novel reliability projection model of semiconductor laser diodes (LD) is presented. By correlating initial thermal characteristics and long-term degradation, a relationship between LD degradation and ambient temperature has been investigated. The proposed model is found to be efficient for the reliability projection of LDs, which requires a thermal characterization only at t=0.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122646729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhancing moisture resistance of PBGA","authors":"Y. C. Teo, E. Wong, T. Lim, Yu Yang, J. Ju","doi":"10.1109/ECTC.1998.678820","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678820","url":null,"abstract":"One of the main package reliability limitations of PBGA is its moisture sensitivity performance, i.e. popcorn failure. The objective of this work is to enhance the moisture resistance of a 35/spl times/35 mm overmolded PBGA by matching its material combination. The approach taken is to correlate the package moisture sensitivity performance with the packaging material properties. JEDEC level 2 moisture sensitivity performance was achieved with two different combinations of materials. The best combination was close to achieving level 1 performance, thereby reinforcing the importance of material matching. Mold compound moisture absorption property has the strongest correlation with package moisture performance. A low value is favourable. For die attach material, the hot and wet adhesion shear strength showed the strongest correlation with package moisture performance. High adhesion shear strength is preferred. Unlike mold compound, the moisture absorption property of die attach material has a significantly weaker correlation.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125148402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Epoxy-based aqueous-processable photodielectric dry film and conductive ViaPlug for PCB build-up and IC packaging","authors":"C. G. González, R. Wessel, S. Padlewski","doi":"10.1109/ECTC.1998.678683","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678683","url":null,"abstract":"DuPont formulated a new generation of photoimageable permanent resists and conductive ViaPlug polymer to be used as building blocks for sequential build-up of PCBs, MCM-Ls, and plastic IC packages. The buzzwords for these structures are HDIS (high density interconnection structures) and microvias. The conventional method of making PCBs and MCM-Ls is a sequential lamination of innerlayer cores or interplanes, followed by at least one mechanical drilling. In this paper we will discuss a new approach of using semi-additive plating which means starting with a multilayer core, mechanically drilling for though hole connection, filling the through-hole with conductive ViaPlug, then adding layers of dielectric to make blind or buried vias for interconnection and routing of circuits, and heat dissipation. The paper will discuss the challenges in each application, relevant industry specifications for each application, and the dielectric and conductor materials properties to meet the challenges. From the viewpoint of technology choices, we will compare photoimaging versus laser ablation and plasma etching. Lastly, we will discuss our reliability data developed internally and in conjunction with several consortia.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125170238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal fatigue reliability analysis of redistributed flip chip assemblies","authors":"B. Vandevelde, E. Beyne","doi":"10.1109/ECTC.1998.678669","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678669","url":null,"abstract":"The thermo-mechanical reliability of redistributed flip chip assemblies is in particular determined by the plastic deformations of the solder joints and by the stresses in the photo-BCB redistribution layers. Finite element simulations and Coffin Manson based reliability models are used to compare the thermal cycling reliability of redistributed and standard flip chip assemblies. The existence of a photosensitive BCB redistribution layer on the chip influences the thermal fatigue of the flip chip assembly. The largest reliability improvement using redistributed chips is achieved by moving the solder joints from the perimeter to the interior of the die resulting in an area array flip chip.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125380505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-domain analysis of PBGA solder joints for structural design optimization","authors":"M. Rassaian, W. Chang, Jung-Chan Lee","doi":"10.1109/ECTC.1998.678917","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678917","url":null,"abstract":"This paper describes the use of stress and strain analysis to accurately predict solder joint fatigue life of plastic ball grid array (PBGA) components under cyclic thermal loading conditions. The finite element analysis (FEA) involved the complete physical make-up of the assembly, including the die adhesive of a typical \"off-the-shelf\" PBGA component. By choosing the appropriate size of the assembly in the multi-domain analysis approach, a considerable saving in computational time was achieved for comparable accuracy to the finite element model (FEM). Three solder ball geometries were selected for the multi-domain models based on different assembly techniques. The strain range of the PBGA solder balls with different geometry under thermomechanical loading were computed and then converted into cycle life through the Coffin-Manson fatigue-life relationship. Experimental assessment of PBGA life cycle using thermochambers is planned to validate the analytical predictions prior to simulating newly designed PBGA solder joint configurations.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125538858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Segawa, M. Ono, S. Musha, Y. Kishimoto, A. Ohashi
{"title":"A CMOS image sensor module applied for a digital still camera utilizing the TOG (TAB On Glass) bonding method","authors":"M. Segawa, M. Ono, S. Musha, Y. Kishimoto, A. Ohashi","doi":"10.1109/ECTC.1998.678853","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678853","url":null,"abstract":"The world's smallest (105/spl times/55/spl times/20 mm) and lightest (130 g) digital still camera has been developed, in which a 330 kpixel CMOS image sensor chip is used as an image sensor. The authors have developed a new thinner and smaller image sensor module, called TOG (TAB On Glass) module, using the ACP (Anisotropic Conductive Paste) interconnection method. The TOG production process was established by obtaining optimum bonding conditions for both optical glass bonding and CMOS chip bonding to the TAB tape. The bonding conditions, including sufficient bonding margins, were mainly studied. The TOG module obtained good imaging properties. It also has a high reliability such as thermal cycle test (-10 to +110/spl deg/C/30 min, 2000 cycles) and the high temperature storage test (60/spl deg/C, 90%RH, 3000 h). The stable production process was confirmed by developing an automatic bonding machine.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Kawamura, K. Hirohata, T. Kawakami, K. Sawada, T. Mino, A. Kurosu, E. Takano, Yoo Hee Yeoul
{"title":"Adhesion integrity evaluation of plastic encapsulated semiconductor package","authors":"N. Kawamura, K. Hirohata, T. Kawakami, K. Sawada, T. Mino, A. Kurosu, E. Takano, Yoo Hee Yeoul","doi":"10.1109/ECTC.1998.678858","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678858","url":null,"abstract":"Plastic encapsulated semiconductor packages may crack if interval delamination occurs during the reflow soldering process, and adhesion integrity evaluation of plastic packages is becoming increasingly important. A new method of estimating the adhesion integrity between epoxy molding resin and silicon chips for plastic packages is proposed. First, three-dimensional stress analysis was carried out to obtain stress distributions in quad flat packages (QFPs) during the reflow soldering process. Next, resin adhesion strength tests were carried out. The shearing load acting on a resin cube molded on a silicon chip was measured, and the maximum shearing load at breakage was obtained. Finally, it was proposed that the stress distributions near the adhesion resin edge of the resin in the test specimen at breakage be used as the criterion for adhesion integrity evaluation of the packages. The adhesion integrity for some QFPs was predicted by comparing the analytical stress distribution in the package and the criterion calculated from the results of the adhesion strength test. The results of reliability tests on the package showed that the new criterion allowed effective evaluation.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124979478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Solid state UV-laser technology for the manufacture of high performance organic modules","authors":"D.B. Noddin, E. Swenson, Y. Sun","doi":"10.1109/ECTC.1998.678802","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678802","url":null,"abstract":"Advances in solid state laser technology have enabled tremendous performance increases in chip packaging technology. Organic composites are now available for high I/O flip chip modules due in part to the size, speed and flexibility of laser via creation methodologies. Generation of the third and fourth harmonics of the fundamental infrared Nd-YAG wavelength enable precision micromachining of alternating layers of organic insulators and metal conductors. The range of available pulse energies at high repetition rate, low M/sup 2/ values and superb pulse stability allows the formation of both high aspect ratio through vias and very small blind vias utilizing similar tools. The ability to fabricate chip packages with through vias, staggered blind vias, or any combination of blind, buried and through vias affords system and chip level design teams the maximum allowable flexibility to optimize performance versus cost. The most fundamental hardware improvements revolve around the conversion efficiency and power stability of Q-switched, lamp pumped Nd-YAG lasers utilizing BBO crystals for harmonic generation. The high pulse energies coupled with excellent beam quality translates into near theoretical focal depth values that in turn allow <50 micron, >7:1 aspect ratio interconnects to be manufactured at defect densities less than 50 ppm. Other advances including improved coatings on crystals and optics and improved thermal management at the rail, result in overall system availability exceeding 85% and via location accuracy of better than +/-20 microns. Future advances are likely to include a migration from lamp pumping to diode pumping, optimization of frequency conversion and laser design for greater power at high repetition rates, multi-rail systems and improved automation. A roadmap for past, current and future laser characteristics as they relate to via qualities and their relative costs will be discussed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130033733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}