1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献_第5页

Intrasystem interconnection in telecommunication platforms using plastic optical fiber 使用塑料光纤的电信平台系统内互连

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678829

G. Grimes, L. L. Blyler, C. J. Sherman, J.S. Nyquist, S. Peck

引用次数: 2

Interconnect simulation using order reduction and scattering parameters 采用降阶和散射参数的互连仿真

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678761

W. Beyene, J. Schutt-Ainé

引用次数: 9

Film chip interconnect systems prepared by wet chemical metallization 湿化学金属化制备薄膜芯片互连系统

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678713

F. Kuchenmeister, M. Bottcher, V. Beyer, S. Thierbach, M. Ekkehard, M. Agater, J. Kickelhain, D. Meier

引用次数: 2

Overmold technology applied to cavity down ultrafine pitch PBGA package 超细螺距PBGA封装的复模工艺

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678734

S. Ouimet, Marie-Claude Paquet

引用次数: 16

Polymer interfacial adhesion in microelectronic assemblies 微电子组件中的聚合物界面粘附

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678682

X. Dai, M. Brillhart, P. Ho

{"title":"Polymer interfacial adhesion in microelectronic assemblies","authors":"X. Dai, M. Brillhart, P. Ho","doi":"10.1109/ECTC.1998.678682","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678682","url":null,"abstract":"The performance requirements of future electronic packages create the need for transition from traditional wire bond connections to advanced technologies such as flip chip on laminate and direct chip attach. These high performance connections utilize a particulate reinforced structural epoxy (underfill) to adhere the chip to the package or board. The integrity of the underfill/silicon chip and underfill/substrate (ceramic or polymer laminates) interfaces are crucial for the reliability of these chip attach methods. This paper presents fracture-mechanics-based experimental and analytical techniques for quantitatively and reproducibly determining the adhesive performance of chip/underfill and polymer substrate/underfill interfaces. The results of the adhesion studies on underfill/passivated silicon and underfill/polymer coated FR4 board interfaces are presented. The effects of different underfill formulations, board coatings and chip passivation layers on underfill interfacial performance are discussed. These techniques can be employed to rapidly evaluate new materials and examine process modification impact on adhesive performance in a wide range of environments.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Pad redistribution technology for flip chip applications 倒装芯片应用的衬垫再分配技术

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678851

C. Tsui, Y. Huang, J.H. Wu

引用次数: 3

Preventing popcorning: what does it cost the industry? 防止爆米花:这个行业要付出什么代价?

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678736

T. Hannibal, A. Singer, L. Nguyen, D. Tracy, D. Giberti

{"title":"Preventing popcorning: what does it cost the industry?","authors":"T. Hannibal, A. Singer, L. Nguyen, D. Tracy, D. Giberti","doi":"10.1109/ECTC.1998.678736","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678736","url":null,"abstract":"Moisture absorption and associated assembly problems become more likely with the proliferation of larger IC packages. Growing technology trends such as Ball Grid Array (BGA) packaging, \"system on a chip\" IC design, and multi-chip modules all drive the industry's move towards these larger package sizes. Board assemblers currently mitigate the yield losses due to \"popcorning\", delamination, and other moisture-related problems by limiting exposure and/or removing the moisture from components that have exceeded their recommended floor life. This paper, part of the Plastic Packaging Consortium effort led by National Semiconductor, assesses the costs to the industry on a per placement basis for delamination prevention. This paper highlights common protocols used at North American assembly facilities to handle moisture-sensitive components. In addition, the cost implications of these procedures to the assemblers are investigated using a method for modeling manufacturing costs, Technical Cost Modeling (TCM). In light of these costs and industry opinions, the opportunity for a moisture resistant packaging solution is discussed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127033640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Signal integrity optimization of high-speed VLSI packages and interconnects 高速VLSI封装和互连的信号完整性优化

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678847

Q. Zhang, F. Wang, M. Nakhla, J. Bandler, R. Biernacki

引用次数: 5

A study of a new flip chip packaging process for diversified bump and land combination 一种新的倒装晶片封装工艺的研究

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678712

M. Mizutani, S. Ito, M. Kuwamura, H. Noro, S. Akizuki, A. Prarhu

{"title":"A study of a new flip chip packaging process for diversified bump and land combination","authors":"M. Mizutani, S. Ito, M. Kuwamura, H. Noro, S. Akizuki, A. Prarhu","doi":"10.1109/ECTC.1998.678712","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678712","url":null,"abstract":"Flip chip packages using plastic substrates are becoming popular in the IC packaging market. However, it still has not been standardized as a real mass production system. We have newly developed a flip chip packaging technology using a nonconductive underfill resin sheet. The process flow of the new flip chip packaging is as follows. First, the underfill sheet is laminated onto substrate. Next, the bumped die is aligned and attached onto substrate which is covered by the underfill sheet under proper heat and pressure. The bumps under the die penetrate the resin and to reach the metal land of the substrate. Finally curing the underfill sheet and metal connection are carried out. We have studied the possibility of applying this packaging technology to a diversified bump and land combination by changing the underfill component and process parameters. The electrical stability and package warpage under several stress test conditions, such as JEDEC Level-3 and TST, have been evaluated in this study. After this evaluation, we found that the packages which have been built with proper resin components and process parameters show good performance for all of these reliability tests almost regardless of bump and land materials.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125219652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

MEMS packaging for micro mirror switches 微镜开关的MEMS封装

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678755

Long-Sun Huang, Shi-sheng Lee, E. Motamedi, M. Wu, C.J. Kim

{"title":"MEMS packaging for micro mirror switches","authors":"Long-Sun Huang, Shi-sheng Lee, E. Motamedi, M. Wu, C.J. Kim","doi":"10.1109/ECTC.1998.678755","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678755","url":null,"abstract":"A new packaging architecture is developed for the hybrid integration of free-space MOEMS (micro-opto-electro-mechanical systems) chip with a silicon micromachined submount. The submount is designed to accommodate various free-space MOEMS chips with minimal active optical alignment, thus reducing the packaging cost. The silicon submount has a central recess to place the MOEMS chip in, four V-grooves for optical fibers, and micropits for micro ball lenses, all bulk micromachined at the same time by a single anisotropic wet etching step. A corner compensation technique was employed to prevent erosion of the convex corners, where different geometries meet. With this packaging scheme, a \"pick-and-drop\" passive hybrid packaging of MOEMS devices becomes possible. The packaged MOEMS device can then be assembled into final product using standard integrated-circuit packages, such as pin-grid-array packages. The vibration test of a packaged micro mirror switch chip was performed to investigate the robustness of the packaging. Neither mechanical degradation or optical error was observed for vibrations up to 100 g's and frequencies from 200 Hz to 10 kHz for over 24 hours.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131715190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30