1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献

{"title":"Intermetallic compound growth on Ni, Au/Ni, and Pd/Ni substrates with Sn/Pb, Sn/Ag, and Sn solders [PWBs]","authors":"H. D. Blair, T. Pan, J. Nicholson","doi":"10.1109/ECTC.1998.678704","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678704","url":null,"abstract":"The growth mechanism of the Ni/sub 3/Sn/sub 4/ intermetallic compound (IMC) during aging was studied with three different solders (100Sn, Sn-3.5Ag, and Sn-37Pb) on three different substrates (Ni, Ni/Au, and Ni/Pd), at the temperatures of 75, 100, 125, and 160/spl deg/C from 1 to 36 days. The growth rates of Ni/sub 3/Sn/sub 4/ with Sn on Ni and Ni/Au substrates were similar, growing to about 6 /spl mu/m after 36 days at 160/spl deg/C, but only to about 1-2 /spl mu/m after 36 days at a temperature below 100/spl deg/C. The growth rate of Ni/sub 3/Sn/sub 4/ with Sn-37Pb on Ni/Au substrate was close to that with Sn for the same substrates. However, the Sn-3.5Ag solder showed a slower growth rate of Ni/sub 3/Sn/sub 4/ on both Ni and Ni/Au substrates, resulting in only about half the thicknesses when compared to Sn on the same substrates. In addition to the Ni/sub 3/Sn/sub 4/ compound, a PdSn/sub 4/ compound was observed on the NiPd substrates. The growth rate of Ni/sub 3/Sn/sub 4/ on the Ni/Pd substrate is much slower than that on either the Ni or the Ni/Au substrate, possibly due to the existence of the PdSn/sub 4/ layer between Ni and the solder. At temperatures lower than 100/spl deg/C, there is hardly any Ni/sub 3/Sn/sub 4/ detected for Sn-3.5Ag and Sn-37Pb solders for up to 36 days. The apparent activation energies, Q, are in the range of 3 to 12.8 Kcal/mole, and Q for Ni/sub 3/Sn/sub 4/ with Sn is the highest for the three solders on both the Ni and Ni/Pd substrates, and those for Sn-3.5Ag the lowest. However, Q for Ni/sub 3/Sn/sub 4/ growth with Sn-3.5Ag is the highest on the Ni/Au substrate. A thick Ni/sub 3/Sn/sub 4/ layer may pose potential reliability issues as evidenced by the fractured morphology of the intermetallics due to a 10.7% volume shrinkage during the transformation from solid phase Sn and Ni to the Ni/sub 3/Sn/sub 4/ compound.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Barium titanate/epoxy composite dielectric materials for integrated thin film capacitors","authors":"S. Liang, S.R. Chong, E. Giannelis","doi":"10.1109/ECTC.1998.678688","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678688","url":null,"abstract":"Integration of passive components into electronic packaging will lead to further structural miniaturization, performance and reliability improvements, as well as cost reduction in the microelectronics industry. To replace the discrete capacitors currently employed in packages with the embedded ones, suitable dielectric materials and thin film processes compatible with the PWB technology are desired. Toward this end, we have been investigating a thin film technology based on barium titanate (BaTiO/sub 3/)/epoxy composites, whose advantages in terms of processability, low processing temperature, and versatility make it quite promising. In this process, the homogeneous dispersion of fine-grained barium titanate into the epoxy matrix was achieved through the surface functionalization of the ceramic powders with a silane coupling agent. Particulate coatings were formulated using the functionalized barium titanate powders, bisphenol A epoxy resin, dicyandiamide, and 2-methylimidazole in an organic solvent. The composite dielectric thin layers were processed on Cu substrates by spinor dip-coating followed by curing at 175/spl deg/C. Electrical measurements on these capacitors demonstrate that, for composite dielectric films containing 60 vol% of barium titanate, a dielectric constant of about 40 at 1 kHz and low loss factors of less than 0.035 over a wide frequency region have been obtained.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122213293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of thermoelastic lamination theory to predict warpage of a symmetric and simply supported printed wiring board during temperature cycling","authors":"Y. Polsky, C. Ume, W. Sutherlin","doi":"10.1109/ECTC.1998.678717","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678717","url":null,"abstract":"The applicability of classical laminated plate theory to the prediction of thermally induced warpage of a printed wiring board is examined in this study. A bare, four-layer printed wiring board without traces has been constructed. The temperature-dependent mechanical properties of the board core materials have been measured. Closed form solutions of the differential equations of equilibrium for the classical lamination theory description of the board are obtained to predict warpage. The model accounts for material property change with temperature, the board's support conditions, and thermal gradients through the board thickness to assess the role of each in the warpage process. The warpage results predicted by the model are then compared to those obtained experimentally, using the shadow-moire technique in a simulated infrared reflow environment, to assess the model's accuracy.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122226669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterisation of the electrical performance of buried capacitors and resistors in low temperature co-fired (LTCC) ceramic","authors":"K. Delaney, J. Barrett, J. Barton, R. Doyle","doi":"10.1109/ECTC.1998.678815","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678815","url":null,"abstract":"This paper describes the electrical characterisation of a novel integrated passive component technology developed using low temperature co-fired ceramic (LTCC) techniques which provides high quality buried capacitors, up to 7.8 nF/cm/sup 2/, and buried resistor materials in the range 100 /spl Omega//sq. to 20 k/spl Omega//sq. The characterisation was undertaken to analyse the components' performance under the individual and combined effects of applied frequency (100 Hz-13 MHz), temperature (-60C to +160C), and DC voltage (-35 volts to +35 volts). The results seen when these applied parameters were varied with regard to one another show complex interactive behaviour which was a function of the materials used. The scope of the work (/spl sim/6500 buried LTCC capacitors and resistors) facilitated analysis of such effects on a statistical level and over a number of material batches. A series of electrical models were completed and two sets of predictive functions were derived for the capacitors and the resistors. The models employed data taken from measurements of cross-sections of a number of different component geometries, and the accuracy of the final models facilitated prediction of process related defects present where manufacturing parameters are not optimised. The predictive functions allow designers to confidently anticipate the electrical performance of the components over the entire working temperature range of the target application.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120978019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of process variables on the reliability of microBGA/sup TM/ package assemblies","authors":"J. Partridge, P. Boysan, B. Surratt, D. Foehringer","doi":"10.1109/ECTC.1998.678742","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678742","url":null,"abstract":"Chip scale packages (CSP) are being introduced as fine-pitch ball array components offering increased product performance and full compatibility with current surface mount assembly operations. A 0.75 mm pitch CSP aimed at the flash memory market is being produced as an alternative to the standard thin small outline package. The current study evaluates the effects of board surface finish and assembly process parameters on the accelerated thermal cycling life of such assemblies. Both daisy chained and functional flash memory MicroBGA/sup TM/ packages are used in a matrix of experiments including high and low solder paste volumes and two surface finishes. In-line solder paste volume measurements are discussed with respect to modern printing technologies and recommendations are made regarding SMT process optimization. Reliability test data are presented following testing at both -40/spl deg/C to 85/spl deg/C and 0/spl deg/C to 100/spl deg/C conditions.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128401706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal oxidation control for enhancement of copper lead frame-EMC adhesion in packaging process","authors":"Byungrok Moon, H. Yoo, K. Sawada","doi":"10.1109/ECTC.1998.678861","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678861","url":null,"abstract":"This study investigates the relationship between oxide layer thickness on lead frame and degree of delamination at the interface of copper lead frame and epoxy molding compound (EMC). It was observed that there is an optimum range of oxide layer thickness within which delamination performance is best. Contrary to previous studies, this range does not only have an upper limit but a lower limit as well. Furthermore, this range varies depending on lead frame type and supplier even though these lead frames are based on the same raw material. Based on these findings the possibility of process control was explored to expose the lead frames to temperatures which will control the oxide layer thickness within the optimum range.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130954062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The execution of aggressive PBGA substrate yield learning in an existing PWB facility","authors":"J. Fuller, E. M. Norton","doi":"10.1109/ECTC.1998.678804","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678804","url":null,"abstract":"As the market for PBGA products explodes and substrate facilities are designed, built, and brought on line, yield learning is vitally important. It is rare that a new product will be introduced at its steady state yield target, necessitating aggressive yield improvement planning. In particular, manufacturers who have converted portions of existing PWB capacity to PBGA product sets will find this to be true. In this paper, the authors articulate the significant challenges manufacturers face ramping up PBGA product. Complex logistics, multiple process flows, multiple customer requirements, aggressive delivery schedules, non-PWB defect mechanisms, non-functionally defined engineering specifications, and a paradigm shift in manufacturing philosophy complicate a product with great intrinsic manufacturing difficulty. This paper reviews in detail the challenges, philosophy and methodology employed to achieve dramatic improvement in PBGA product yields. The paper also includes suggestions for changes in business process procedures to ensure yield learning is engrained as part of any PBGA product introduction. A detailed system of matrix management that utilized process control as the foundation for yield improvement is included. The organization structure, review cycle, improvement road maps, yield tracking and data analysis are discussed in detail. Overall yield improvement results, along with several representative products, are generically shared to validate the philosophy and methodology employed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129608516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adhesives for optical devices","authors":"N. Murata","doi":"10.1109/ECTC.1998.678869","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678869","url":null,"abstract":"Three types of UV-curable adhesives, a room temperature curing sealant and a hot-melt adhesive for the fabrication of optical communications devices were developed. (1) Using new epoxies, acrylates and vinyl sulfide containing fluorine, bromine and sulfur, the refractive indices of UV-curable transparent adhesives can be controlled, in the range 1.41-1.70 within /spl plusmn/0.005 with a high light transmittance of 80-90% at a wavelength of 1.3 /spl mu/m. They possess an excellent refractive index matching that of optical glass and optical fibers. They have high adhesive strength and good durability. (2) The UV-curable precision adhesive has an extremely low volume shrinkage of 1.2% during curing and the cured adhesive has a low thermal expansion coefficient of <2/spl times/10/sup -5///spl deg/C. Therefore, they can be used in the fabrication of optical devices that require sub-micron positioning accuracy. (3) The UV-curable thermal-resistant adhesive exhibits a high glass transition temperature of more than 200/spl deg/C. This adhesive has applications in the assembly of optical components that require higher heat-resistance. (4) The water permeability of the moisture-protected adhesive sealant is an extremely small 8/spl times/10/sup -9/ cc cm/cm/sup 2//cmHg/sec at a high temperature of 75/spl deg/C. The optical excess loss of sealing fiber due to the microbending during curing and temperature cycling (+85/spl deg/C to -40/spl deg/C) is negligibly small (less than 0.01 dB). (5) The water-resistant hot-melt adhesive for reinforcing optical-fiber splices applied to quartz glass by hot-press for 3 minutes at 130/spl deg/C provides excellent adhesion. The peel strength is maintained for over one year after immersion in water of 60/spl deg/C. These qualities of the developed UV-curable adhesives and the new sealants are advantageous for achieving low-cost and high reliability optical devices.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132359878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correlation of flip chip underfill process parameters and material properties with in-process stress generation","authors":"P. Palaniappan, P. J. Selman, D. Baldwin, C. Wong","doi":"10.1109/ECTC.1998.678805","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678805","url":null,"abstract":"Package design is headed towards fewer levels of packaging and one such design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). The interconnection technique utilizes chips having solder bumps on each bond pad. The bumped chips are aligned to the substrate traces and attached using eutectic solder. As the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between these materials. To overcome this problem, a rigid encapsulant is introduced between the chip and the substrate which reduces the actual CTE mismatch thus reducing the effective stresses experienced by the solder interconnects and significantly improving long term reliability. The underfill material however, does introduce a high level of mechanical stress in the silicon die. The induced stress in the assembly is a function of the underfill material utilized, the assembly process used and the curing parameters. Therefore, the selection of underfill material is critical to achieving the desired performance and reliability. The effect of encapsulation material on the mechanical stress induced in a flip chip assembly during underfill cure was presented in previous papers (Palaniappan and Baldwin, 1997). This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing. The goal of this work is to determine the fundamental effects of assembly process history on stresses generated in low cost flip chip assemblies ultimately linking these to reliability performance. The objectives are to characterize the material properties of underfills processed under varying assembly conditions, perform in-situ stress measurements in the flip chip assemblies processed under the same conditions to characterize the stress distribution and maximum stress at the chip/underfill interface and to correlate material properties with the residual stresses as a function of assembly process parameters. In this work, the ATC04 assembly test chip from Sandia National Laboratories was used to analyze commercial underfill processed under different cure parameters. Underfill samples were cured in situ during test vehicle assembly process to determine the glass transition temperature, T/sub g/, storage modulus, G' and the coefficient of thermal expansion, CTE. Correlation between the underfill material properties, the relative stresses produced during cure, and the cure parameters are made.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132420003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Plastic VCSEL array packaging and high density polymer waveguides for board and backplane optical interconnect","authors":"Y.S. Liu, R. Wojnarowski, W. Hennessy, P. Piacente, J. Rowlette, M. Kadar-Kallen, J. Stack, Yue Liu, A. Peczalski, A. Nahata, J. Yardley","doi":"10.1109/ECTC.1998.678832","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678832","url":null,"abstract":"The technical approach and progress achieved under the Polymer Optical Interconnect Technology (POINT) program are described in this paper. The POINT program is a collaborative effort among GE, Honeywell, AMP, AlliedSignal, Columbia University, and University of California at San Diego (UCSD), sponsored by DARPA/ETO, to develop affordable optoelectronic packaging and interconnect technologies for board and backplane applications. Specifically, progress is reported on (a) development of batch-operated plastic VCSEL array packaging technology using planar fabrication, (b) demonstration of high-density optical interconnects for board and backplane applications using polymer waveguides to a length of 50 cm at an I/O density of 250 channels per inch, (c) development of low-loss optical polymer waveguides with loss less than 0.1 dB/cm at 850 nm, and (d) development of passive alignment processes for efficient coupling between a VCSEL array and polymer waveguides. Significant progress has also been made under the POINT program at Columbia University, in applying CAD tools to simulate multimode-guided wave systems and, at UCSD, to assist mechanical and thermal design in optoelectronic packaging.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114264622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}