1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献

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A new analytic model of simultaneous switching noise in CMOS systems 一种新的CMOS系统同步开关噪声分析模型
Hye-Ran Cha, O. Kwon
{"title":"A new analytic model of simultaneous switching noise in CMOS systems","authors":"Hye-Ran Cha, O. Kwon","doi":"10.1109/ECTC.1998.678759","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678759","url":null,"abstract":"A new accurate and analytic model for SSN (Simultaneous Switching Noise) on both power supply and ground lines in CMOS circuit is presented. While most prior works were concentrated on the case in which all the drivers switch at the same time, this paper considers the influences of switching of the some drivers on the quiet drivers, and reveals that the proposed model is more accurate than the existing ones in this case. This result can provide some useful design guide of CMOS driver circuits. We confirmed that the proposed model is more accurate than the existing ones through HSPICE simulation using Level 28 MOS model.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127644656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A novel flip chip technology using non-conductive resin sheet 采用不导电树脂片的新型倒装芯片技术
Satoshi Ito, Masaki Mizutani, H. Noro, M. Kuwamura, Ashok Prabhu, Nitto Denko
{"title":"A novel flip chip technology using non-conductive resin sheet","authors":"Satoshi Ito, Masaki Mizutani, H. Noro, M. Kuwamura, Ashok Prabhu, Nitto Denko","doi":"10.1109/ECTC.1998.678843","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678843","url":null,"abstract":"A novel flip chip packaging technology using non-conductive resin sheet has been studied. The process flow of this new packaging system is as follows. First, epoxy base resin sheet is laminated onto substrate to cover the substrate surface including land electrodes. Bumped chip alignment and attachment has done through the resin sheet, in the second stage with pressure and temperature. The bumps under the chip penetrate with removing resin sheet material and eventually reaching to the metal land of the substrate in this process. Metal connection and curing of the interface resin have completed in the third stage. This new process has big potential to make flip chip package simple compared with current flip chip packaging process using liquid resin with dispensing system. The through put time can be reduced to less than 10 seconds/units in actual model case even large flip chip package which has over 15/spl times/15 (mm) square area IC chip. The other advantages are thermal stability of material in the process, moisture related performance, and warpage control performance. For current underfill process we have only choice to use anhydride type resin system which has many disadvantaged on that. This new process made it possible to introduce moisture and thermally stable epoxy resin with phenol curing system for flip chip packaging. Drastic process ability improvement can be achieved by the new process and material. As a typical improvement of thermal shock performance, it was confirmed that the life of chip damage becomes over 10 times longer by flip chip bonding parameters which can be controlled only by this new flip chip packaging process.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127661031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Proposed strategies for microelectronic packaging education for next generation engineers 新一代微电子封装工程师的教育策略
B.C. Kim
{"title":"Proposed strategies for microelectronic packaging education for next generation engineers","authors":"B.C. Kim","doi":"10.1109/ECTC.1998.678748","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678748","url":null,"abstract":"Discusses several proposed strategies to integrate microelectronic packaging education in the electrical engineering curriculum at Tufts University. The strategies include some of the traditional initiatives and a novel approach for undergraduates, graduates and professionals in industry.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121453734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low cost MCM-L fiber-optic transmitter package 低成本的MCM-L光纤发射机包
H.G. Kellzi
{"title":"Low cost MCM-L fiber-optic transmitter package","authors":"H.G. Kellzi","doi":"10.1109/ECTC.1998.678725","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678725","url":null,"abstract":"A true implementation of MCM-L is accomplished by converting an existing fiber optic transmitter (FOTR) module fabricated by conventional technology in MCM-C, where high reliability has imposed hermeticity and established military standards and requirements. The MCM-L rendition provides a lower cost approach satisfying current budgets and high reliability without hermeticity. This MCM-L FOTR utilizes the latest laminate technological advances in order to achieve artwork routing parity of MCM-C, with comparable features to provide high density and miniaturization advanced microelectronic packaging that was not possible up until recently. Complete Chip on Board (COB) has been utilized to further advance miniaturization, also introducing flex input/output (I/O) leads integral to the MCM-L substrate. Extensive tests conducted after encapsulation providing excellent results both functionally and environmentally.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129144487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Intrasystem interconnection in telecommunication platforms using plastic optical fiber 使用塑料光纤的电信平台系统内互连
G. Grimes, L. L. Blyler, C. J. Sherman, J.S. Nyquist, S. Peck
{"title":"Intrasystem interconnection in telecommunication platforms using plastic optical fiber","authors":"G. Grimes, L. L. Blyler, C. J. Sherman, J.S. Nyquist, S. Peck","doi":"10.1109/ECTC.1998.678829","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678829","url":null,"abstract":"Large telecommunication switching and transmission platforms have massive interconnection requirements which are in the 1 Tb/s range and growing rapidly. Plastic optical fiber technology shows promise as a replacement for both metallic interconnection and glass optical fiber interconnection. The high bandwidth characteristics of graded index plastic optical fiber (GI POF) are particularly attractive in these applications which require high reliability and high bandwidth interconnection over short distances.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128449606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Interconnect simulation using order reduction and scattering parameters 采用降阶和散射参数的互连仿真
W. Beyene, J. Schutt-Ainé
{"title":"Interconnect simulation using order reduction and scattering parameters","authors":"W. Beyene, J. Schutt-Ainé","doi":"10.1109/ECTC.1998.678761","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678761","url":null,"abstract":"This paper demonstrates the use of scattering parameters for efficient and accurate simulation of transmission lines. First, a low-order rational approximation scheme is applied to the s parameters of the line system, next an appropriate reference system is chosen to optimize the formulation. Finally, the low-order rational approximations of the scattering parameters are directly implemented in conventional time-domain simulator using recursive convolution. Experimental results are used to validate the computer simulations.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116792809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Film chip interconnect systems prepared by wet chemical metallization 湿化学金属化制备薄膜芯片互连系统
F. Kuchenmeister, M. Bottcher, V. Beyer, S. Thierbach, M. Ekkehard, M. Agater, J. Kickelhain, D. Meier
{"title":"Film chip interconnect systems prepared by wet chemical metallization","authors":"F. Kuchenmeister, M. Bottcher, V. Beyer, S. Thierbach, M. Ekkehard, M. Agater, J. Kickelhain, D. Meier","doi":"10.1109/ECTC.1998.678713","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678713","url":null,"abstract":"A novel low cost flip-chip like microelectronics packaging technology for bonding integrated circuits to polymer foils has been developed. The chip with the active side facing the polyimide foil is attached by an pre-deposited adhesive. Excimer laser micromachining technique for via hole fabrication to the bond pads was employed. Two different wet chemical metallization processes were investigated for electrical connecting the bond pads. The conductive patterns were fabricated by additive or semiadditive processing technique. Besides the detailed description of the major process steps, results of initial reliability investigations are presented.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115545174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Overmold technology applied to cavity down ultrafine pitch PBGA package 超细螺距PBGA封装的复模工艺
S. Ouimet, Marie-Claude Paquet
{"title":"Overmold technology applied to cavity down ultrafine pitch PBGA package","authors":"S. Ouimet, Marie-Claude Paquet","doi":"10.1109/ECTC.1998.678734","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678734","url":null,"abstract":"The transfer molding technology is normally used for leadframe type packages and chip-up PBGA (Plastic Ball Grid Array) packages. This technology has been applied to cavity down PBGA packages where, normally, a liquid epoxy is dispensed by a needle in the cavity in order to cover the device and gold wires without exceeding the solder ball height plane. The new encapsulation approach using transfer molding process as well as the debug/qualification method and results using an ultrafine pitch wirebond PBGA process are described.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114574279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Polymer interfacial adhesion in microelectronic assemblies 微电子组件中的聚合物界面粘附
X. Dai, M. Brillhart, P. Ho
{"title":"Polymer interfacial adhesion in microelectronic assemblies","authors":"X. Dai, M. Brillhart, P. Ho","doi":"10.1109/ECTC.1998.678682","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678682","url":null,"abstract":"The performance requirements of future electronic packages create the need for transition from traditional wire bond connections to advanced technologies such as flip chip on laminate and direct chip attach. These high performance connections utilize a particulate reinforced structural epoxy (underfill) to adhere the chip to the package or board. The integrity of the underfill/silicon chip and underfill/substrate (ceramic or polymer laminates) interfaces are crucial for the reliability of these chip attach methods. This paper presents fracture-mechanics-based experimental and analytical techniques for quantitatively and reproducibly determining the adhesive performance of chip/underfill and polymer substrate/underfill interfaces. The results of the adhesion studies on underfill/passivated silicon and underfill/polymer coated FR4 board interfaces are presented. The effects of different underfill formulations, board coatings and chip passivation layers on underfill interfacial performance are discussed. These techniques can be employed to rapidly evaluate new materials and examine process modification impact on adhesive performance in a wide range of environments.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Pad redistribution technology for flip chip applications 倒装芯片应用的衬垫再分配技术
C. Tsui, Y. Huang, J.H. Wu
{"title":"Pad redistribution technology for flip chip applications","authors":"C. Tsui, Y. Huang, J.H. Wu","doi":"10.1109/ECTC.1998.678851","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678851","url":null,"abstract":"Flip chip applications typically involve solder joint interconnections between the device chip and different substrates. In most cases, the I/O's on the device chip require to be relocated to a new format such as area array in order to match the corresponding pad locations on the substrate. In this paper, we describe one implementation of the pad redistribution technology, using aluminium interconnect lines, a photosensitive polyimide insulating layer and a wettable layer of underbump metallization (UBM) for the subsequent solder bumping applications. A test vehicle employing the flip chip on board (FCOB) assembly was fabricated and subjected to the thermal cycling reliability test. A useful simulation model was applied to understand the solder joint reliability in FCOB.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126642873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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