1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献_第8页

Preventing popcorning: what does it cost the industry? 防止爆米花:这个行业要付出什么代价?

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678736

T. Hannibal, A. Singer, L. Nguyen, D. Tracy, D. Giberti

{"title":"Preventing popcorning: what does it cost the industry?","authors":"T. Hannibal, A. Singer, L. Nguyen, D. Tracy, D. Giberti","doi":"10.1109/ECTC.1998.678736","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678736","url":null,"abstract":"Moisture absorption and associated assembly problems become more likely with the proliferation of larger IC packages. Growing technology trends such as Ball Grid Array (BGA) packaging, \"system on a chip\" IC design, and multi-chip modules all drive the industry's move towards these larger package sizes. Board assemblers currently mitigate the yield losses due to \"popcorning\", delamination, and other moisture-related problems by limiting exposure and/or removing the moisture from components that have exceeded their recommended floor life. This paper, part of the Plastic Packaging Consortium effort led by National Semiconductor, assesses the costs to the industry on a per placement basis for delamination prevention. This paper highlights common protocols used at North American assembly facilities to handle moisture-sensitive components. In addition, the cost implications of these procedures to the assemblers are investigated using a method for modeling manufacturing costs, Technical Cost Modeling (TCM). In light of these costs and industry opinions, the opportunity for a moisture resistant packaging solution is discussed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127033640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Signal integrity optimization of high-speed VLSI packages and interconnects 高速VLSI封装和互连的信号完整性优化

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678847

Q. Zhang, F. Wang, M. Nakhla, J. Bandler, R. Biernacki

引用次数: 5

A study of a new flip chip packaging process for diversified bump and land combination 一种新的倒装晶片封装工艺的研究

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678712

M. Mizutani, S. Ito, M. Kuwamura, H. Noro, S. Akizuki, A. Prarhu

{"title":"A study of a new flip chip packaging process for diversified bump and land combination","authors":"M. Mizutani, S. Ito, M. Kuwamura, H. Noro, S. Akizuki, A. Prarhu","doi":"10.1109/ECTC.1998.678712","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678712","url":null,"abstract":"Flip chip packages using plastic substrates are becoming popular in the IC packaging market. However, it still has not been standardized as a real mass production system. We have newly developed a flip chip packaging technology using a nonconductive underfill resin sheet. The process flow of the new flip chip packaging is as follows. First, the underfill sheet is laminated onto substrate. Next, the bumped die is aligned and attached onto substrate which is covered by the underfill sheet under proper heat and pressure. The bumps under the die penetrate the resin and to reach the metal land of the substrate. Finally curing the underfill sheet and metal connection are carried out. We have studied the possibility of applying this packaging technology to a diversified bump and land combination by changing the underfill component and process parameters. The electrical stability and package warpage under several stress test conditions, such as JEDEC Level-3 and TST, have been evaluated in this study. After this evaluation, we found that the packages which have been built with proper resin components and process parameters show good performance for all of these reliability tests almost regardless of bump and land materials.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125219652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

MEMS packaging for micro mirror switches 微镜开关的MEMS封装

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678755

Long-Sun Huang, Shi-sheng Lee, E. Motamedi, M. Wu, C.J. Kim

{"title":"MEMS packaging for micro mirror switches","authors":"Long-Sun Huang, Shi-sheng Lee, E. Motamedi, M. Wu, C.J. Kim","doi":"10.1109/ECTC.1998.678755","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678755","url":null,"abstract":"A new packaging architecture is developed for the hybrid integration of free-space MOEMS (micro-opto-electro-mechanical systems) chip with a silicon micromachined submount. The submount is designed to accommodate various free-space MOEMS chips with minimal active optical alignment, thus reducing the packaging cost. The silicon submount has a central recess to place the MOEMS chip in, four V-grooves for optical fibers, and micropits for micro ball lenses, all bulk micromachined at the same time by a single anisotropic wet etching step. A corner compensation technique was employed to prevent erosion of the convex corners, where different geometries meet. With this packaging scheme, a \"pick-and-drop\" passive hybrid packaging of MOEMS devices becomes possible. The packaged MOEMS device can then be assembled into final product using standard integrated-circuit packages, such as pin-grid-array packages. The vibration test of a packaged micro mirror switch chip was performed to investigate the robustness of the packaging. Neither mechanical degradation or optical error was observed for vibrations up to 100 g's and frequencies from 200 Hz to 10 kHz for over 24 hours.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131715190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Intermetallic compound growth on Ni, Au/Ni, and Pd/Ni substrates with Sn/Pb, Sn/Ag, and Sn solders [PWBs] 用Sn/Pb、Sn/Ag和Sn焊料在Ni、Au/Ni和Pd/Ni基片上生长金属间化合物[PWBs]

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678704

H. D. Blair, T. Pan, J. Nicholson

{"title":"Intermetallic compound growth on Ni, Au/Ni, and Pd/Ni substrates with Sn/Pb, Sn/Ag, and Sn solders [PWBs]","authors":"H. D. Blair, T. Pan, J. Nicholson","doi":"10.1109/ECTC.1998.678704","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678704","url":null,"abstract":"The growth mechanism of the Ni/sub 3/Sn/sub 4/ intermetallic compound (IMC) during aging was studied with three different solders (100Sn, Sn-3.5Ag, and Sn-37Pb) on three different substrates (Ni, Ni/Au, and Ni/Pd), at the temperatures of 75, 100, 125, and 160/spl deg/C from 1 to 36 days. The growth rates of Ni/sub 3/Sn/sub 4/ with Sn on Ni and Ni/Au substrates were similar, growing to about 6 /spl mu/m after 36 days at 160/spl deg/C, but only to about 1-2 /spl mu/m after 36 days at a temperature below 100/spl deg/C. The growth rate of Ni/sub 3/Sn/sub 4/ with Sn-37Pb on Ni/Au substrate was close to that with Sn for the same substrates. However, the Sn-3.5Ag solder showed a slower growth rate of Ni/sub 3/Sn/sub 4/ on both Ni and Ni/Au substrates, resulting in only about half the thicknesses when compared to Sn on the same substrates. In addition to the Ni/sub 3/Sn/sub 4/ compound, a PdSn/sub 4/ compound was observed on the NiPd substrates. The growth rate of Ni/sub 3/Sn/sub 4/ on the Ni/Pd substrate is much slower than that on either the Ni or the Ni/Au substrate, possibly due to the existence of the PdSn/sub 4/ layer between Ni and the solder. At temperatures lower than 100/spl deg/C, there is hardly any Ni/sub 3/Sn/sub 4/ detected for Sn-3.5Ag and Sn-37Pb solders for up to 36 days. The apparent activation energies, Q, are in the range of 3 to 12.8 Kcal/mole, and Q for Ni/sub 3/Sn/sub 4/ with Sn is the highest for the three solders on both the Ni and Ni/Pd substrates, and those for Sn-3.5Ag the lowest. However, Q for Ni/sub 3/Sn/sub 4/ growth with Sn-3.5Ag is the highest on the Ni/Au substrate. A thick Ni/sub 3/Sn/sub 4/ layer may pose potential reliability issues as evidenced by the fractured morphology of the intermetallics due to a 10.7% volume shrinkage during the transformation from solid phase Sn and Ni to the Ni/sub 3/Sn/sub 4/ compound.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 50

Barium titanate/epoxy composite dielectric materials for integrated thin film capacitors 集成薄膜电容器用钛酸钡/环氧复合介电材料

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678688

S. Liang, S.R. Chong, E. Giannelis

{"title":"Barium titanate/epoxy composite dielectric materials for integrated thin film capacitors","authors":"S. Liang, S.R. Chong, E. Giannelis","doi":"10.1109/ECTC.1998.678688","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678688","url":null,"abstract":"Integration of passive components into electronic packaging will lead to further structural miniaturization, performance and reliability improvements, as well as cost reduction in the microelectronics industry. To replace the discrete capacitors currently employed in packages with the embedded ones, suitable dielectric materials and thin film processes compatible with the PWB technology are desired. Toward this end, we have been investigating a thin film technology based on barium titanate (BaTiO/sub 3/)/epoxy composites, whose advantages in terms of processability, low processing temperature, and versatility make it quite promising. In this process, the homogeneous dispersion of fine-grained barium titanate into the epoxy matrix was achieved through the surface functionalization of the ceramic powders with a silane coupling agent. Particulate coatings were formulated using the functionalized barium titanate powders, bisphenol A epoxy resin, dicyandiamide, and 2-methylimidazole in an organic solvent. The composite dielectric thin layers were processed on Cu substrates by spinor dip-coating followed by curing at 175/spl deg/C. Electrical measurements on these capacitors demonstrate that, for composite dielectric films containing 60 vol% of barium titanate, a dielectric constant of about 40 at 1 kHz and low loss factors of less than 0.035 over a wide frequency region have been obtained.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122213293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

Application of thermoelastic lamination theory to predict warpage of a symmetric and simply supported printed wiring board during temperature cycling 应用热弹性层合理论预测对称简支印刷线路板在温度循环过程中的翘曲

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678717

Y. Polsky, C. Ume, W. Sutherlin

引用次数: 5

Characterisation of the electrical performance of buried capacitors and resistors in low temperature co-fired (LTCC) ceramic 低温共烧(LTCC)陶瓷中埋地电容器和电阻电性能的表征

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678815

K. Delaney, J. Barrett, J. Barton, R. Doyle

{"title":"Characterisation of the electrical performance of buried capacitors and resistors in low temperature co-fired (LTCC) ceramic","authors":"K. Delaney, J. Barrett, J. Barton, R. Doyle","doi":"10.1109/ECTC.1998.678815","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678815","url":null,"abstract":"This paper describes the electrical characterisation of a novel integrated passive component technology developed using low temperature co-fired ceramic (LTCC) techniques which provides high quality buried capacitors, up to 7.8 nF/cm/sup 2/, and buried resistor materials in the range 100 /spl Omega//sq. to 20 k/spl Omega//sq. The characterisation was undertaken to analyse the components' performance under the individual and combined effects of applied frequency (100 Hz-13 MHz), temperature (-60C to +160C), and DC voltage (-35 volts to +35 volts). The results seen when these applied parameters were varied with regard to one another show complex interactive behaviour which was a function of the materials used. The scope of the work (/spl sim/6500 buried LTCC capacitors and resistors) facilitated analysis of such effects on a statistical level and over a number of material batches. A series of electrical models were completed and two sets of predictive functions were derived for the capacitors and the resistors. The models employed data taken from measurements of cross-sections of a number of different component geometries, and the accuracy of the final models facilitated prediction of process related defects present where manufacturing parameters are not optimised. The predictive functions allow designers to confidently anticipate the electrical performance of the components over the entire working temperature range of the target application.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120978019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Influence of process variables on the reliability of microBGA/sup TM/ package assemblies 工艺变量对microBGA/sup TM/封装组件可靠性的影响

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678742

J. Partridge, P. Boysan, B. Surratt, D. Foehringer

引用次数: 5

Optimal oxidation control for enhancement of copper lead frame-EMC adhesion in packaging process 优化氧化控制以提高封装过程中铜引线框架- emc的附着力

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI: 10.1109/ECTC.1998.678861

Byungrok Moon, H. Yoo, K. Sawada

引用次数: 15