1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)最新文献

{"title":"The execution of aggressive PBGA substrate yield learning in an existing PWB facility","authors":"J. Fuller, E. M. Norton","doi":"10.1109/ECTC.1998.678804","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678804","url":null,"abstract":"As the market for PBGA products explodes and substrate facilities are designed, built, and brought on line, yield learning is vitally important. It is rare that a new product will be introduced at its steady state yield target, necessitating aggressive yield improvement planning. In particular, manufacturers who have converted portions of existing PWB capacity to PBGA product sets will find this to be true. In this paper, the authors articulate the significant challenges manufacturers face ramping up PBGA product. Complex logistics, multiple process flows, multiple customer requirements, aggressive delivery schedules, non-PWB defect mechanisms, non-functionally defined engineering specifications, and a paradigm shift in manufacturing philosophy complicate a product with great intrinsic manufacturing difficulty. This paper reviews in detail the challenges, philosophy and methodology employed to achieve dramatic improvement in PBGA product yields. The paper also includes suggestions for changes in business process procedures to ensure yield learning is engrained as part of any PBGA product introduction. A detailed system of matrix management that utilized process control as the foundation for yield improvement is included. The organization structure, review cycle, improvement road maps, yield tracking and data analysis are discussed in detail. Overall yield improvement results, along with several representative products, are generically shared to validate the philosophy and methodology employed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129608516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Adhesives for optical devices","authors":"N. Murata","doi":"10.1109/ECTC.1998.678869","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678869","url":null,"abstract":"Three types of UV-curable adhesives, a room temperature curing sealant and a hot-melt adhesive for the fabrication of optical communications devices were developed. (1) Using new epoxies, acrylates and vinyl sulfide containing fluorine, bromine and sulfur, the refractive indices of UV-curable transparent adhesives can be controlled, in the range 1.41-1.70 within /spl plusmn/0.005 with a high light transmittance of 80-90% at a wavelength of 1.3 /spl mu/m. They possess an excellent refractive index matching that of optical glass and optical fibers. They have high adhesive strength and good durability. (2) The UV-curable precision adhesive has an extremely low volume shrinkage of 1.2% during curing and the cured adhesive has a low thermal expansion coefficient of <2/spl times/10/sup -5///spl deg/C. Therefore, they can be used in the fabrication of optical devices that require sub-micron positioning accuracy. (3) The UV-curable thermal-resistant adhesive exhibits a high glass transition temperature of more than 200/spl deg/C. This adhesive has applications in the assembly of optical components that require higher heat-resistance. (4) The water permeability of the moisture-protected adhesive sealant is an extremely small 8/spl times/10/sup -9/ cc cm/cm/sup 2//cmHg/sec at a high temperature of 75/spl deg/C. The optical excess loss of sealing fiber due to the microbending during curing and temperature cycling (+85/spl deg/C to -40/spl deg/C) is negligibly small (less than 0.01 dB). (5) The water-resistant hot-melt adhesive for reinforcing optical-fiber splices applied to quartz glass by hot-press for 3 minutes at 130/spl deg/C provides excellent adhesion. The peel strength is maintained for over one year after immersion in water of 60/spl deg/C. These qualities of the developed UV-curable adhesives and the new sealants are advantageous for achieving low-cost and high reliability optical devices.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132359878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correlation of flip chip underfill process parameters and material properties with in-process stress generation","authors":"P. Palaniappan, P. J. Selman, D. Baldwin, C. Wong","doi":"10.1109/ECTC.1998.678805","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678805","url":null,"abstract":"Package design is headed towards fewer levels of packaging and one such design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). The interconnection technique utilizes chips having solder bumps on each bond pad. The bumped chips are aligned to the substrate traces and attached using eutectic solder. As the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between these materials. To overcome this problem, a rigid encapsulant is introduced between the chip and the substrate which reduces the actual CTE mismatch thus reducing the effective stresses experienced by the solder interconnects and significantly improving long term reliability. The underfill material however, does introduce a high level of mechanical stress in the silicon die. The induced stress in the assembly is a function of the underfill material utilized, the assembly process used and the curing parameters. Therefore, the selection of underfill material is critical to achieving the desired performance and reliability. The effect of encapsulation material on the mechanical stress induced in a flip chip assembly during underfill cure was presented in previous papers (Palaniappan and Baldwin, 1997). This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing. The goal of this work is to determine the fundamental effects of assembly process history on stresses generated in low cost flip chip assemblies ultimately linking these to reliability performance. The objectives are to characterize the material properties of underfills processed under varying assembly conditions, perform in-situ stress measurements in the flip chip assemblies processed under the same conditions to characterize the stress distribution and maximum stress at the chip/underfill interface and to correlate material properties with the residual stresses as a function of assembly process parameters. In this work, the ATC04 assembly test chip from Sandia National Laboratories was used to analyze commercial underfill processed under different cure parameters. Underfill samples were cured in situ during test vehicle assembly process to determine the glass transition temperature, T/sub g/, storage modulus, G' and the coefficient of thermal expansion, CTE. Correlation between the underfill material properties, the relative stresses produced during cure, and the cure parameters are made.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132420003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assembly-level reliability characterization of chip-scale packages","authors":"P. Lall, K. Banerji","doi":"10.1109/ECTC.1998.678738","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678738","url":null,"abstract":"The reliability of the Elastomer-on-Flex Interposer Chip-Scale Package has been studied under thermal fatigue, out-of-plane deformation, humidity and thermal aging. Two versions of the Elastomer-on-Flex Interposer CSP (from a single source) have been characterized in this study-the 48-pin and 40-pin. Both the 40-bump and 48-bump versions have ball 0.3 mm (11.81 mils) in diameter solder balls at 0.75 mm pitch. Non-linear finite element models have been used to identify and predict the dominant failure mechanisms. The model predictions have been verified with accelerated test data. The results for all the dominant failure mechanisms have been bench-marked against existing technologies including overmolded PBGAs and rigid substrate flip-chip BGAs.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114909546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal dissipation analysis in flip chip on board and chip on board assemblies","authors":"D. Baldwin, J. T. Beerensson","doi":"10.1109/ECTC.1998.678674","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678674","url":null,"abstract":"Direct chip attach packaging technologies are finding increasing application in electronics manufacturing particularly in telecommunications and consumer electronics. In these systems, bare die with bumped interconnect bond pads are assembled in a flip chip configuration (i.e., active face down) directly to low-cost organic substrates. In the current work, thermal management of three direct chip attach technologies is investigated. Experimental measurements are conducted exploring the junction-to-ambient thermal resistance and thermal dissipation paths for three interconnect technologies including solder attach, anisotropic adhesive attach, and isotropic adhesive attach. A first order chip-scale thermal design model is developed for flip chip assemblies exhibiting good agreement with the experimental measurements.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116820010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new technique for high frequency characterization of capacitors","authors":"Y. Li, D. Figueroa, J.P. Rodriguez, L. Huang, J. Liao, M. Taniguchi, J. Canner, T. Kondo","doi":"10.1109/ECTC.1998.678924","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678924","url":null,"abstract":"To improve the accuracy for high frequency characterization of capacitors with very low inductance values, a technique is developed. The first part of the technique requires a standard calibration for a network analyzer. Then s-parameter measurements for test fixtures and adapters are measured. A high frequency circuit model for every connector or test fixture from the calibrated port to the device under test (DUT) is then de-embedded one at a time, using the measured data as a reference and each time adding in the previously de-embedded circuit model. The difference between the measured data and the simulated data is forced to be less than 1%. This stringent requirement is necessary for obtaining the high accuracy equivalent series inductance (ESL) and resistance (ESR). The requirement also guarantees the accuracy of high frequency parasitic capacitance and resistance of a capacitor. After the high frequency circuit models for all test fixtures and adapters are found, s-parameter measurements for a capacitor mounted on a test fixture with an adapter are measured. When the circuit models for the test fixture and adapter are put together and the whole system is matched to the measured s-parameter data for the whole system, the circuit model of a capacitor has been found. In this paper, two new capacitor models and several discontinuity models are also reported. The new capacitor models are valid for the entire frequency range. The discontinuity models are fully consistent with the real physical structure of test fixtures. Different capacitors from various suppliers are characterized and the high frequency circuit models are also provided.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Introduction to electronic packaging: an undergraduate textbook","authors":"R. Tummala","doi":"10.1109/ECTC.1998.678768","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678768","url":null,"abstract":"An undergraduate text book that introduces the subject of packaging in a cross-discipline and system-level fashion is proposed. It will be authored by some of the leading academic and industry experts from around the world. The proposed chapter topics include: (1) what is electronic packaging? (its importance and its markets); (2) technology drivers; (3) electrical design fundamentals; (4) thermo-mechanical design fundamentals; (5) packaging materials and processes; (6) single chip packages; (7) multi chip packages; (8) chip assembly; (9) printed wiring board (PWB); (10) chip-to-board connections; (11) discrete components; (12) optoelectronic packaging; (13) RF electronics; (14) sealing and encapsulation; (15) electrical testing; and (16) reliability.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Packaging for a 40-channel parallel optical interconnection module with an over 25-Gb/s throughput","authors":"K. Katsura, M. Usui, N. Sato, A. Ohki, N. Tanaka, N. Matsuura, T. Kagawa, K. Tateno, M. Hikita, R. Yoshimura, Y. Ando","doi":"10.1109/ECTC.1998.678792","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678792","url":null,"abstract":"NTT is currently working on a project aimed at developing an interconnection module which has high throughput and is both compact and cost-effective. This project is called \"parallel interboard optical interconnection technology\", or \"ParaBIT\". The ParaBIT module being developed as the first step in this project is a front-end module with 40 channels, throughput of over 25 Gb/s, and transmission over 100 m along multimode fibers. One major feature of this module is the use of vertical-cavity surface-emitting laser (VCSEL) arrays as very cost-effective light sources. These arrays also enable a packaging structure that includes transmitter and receiver in one package. To achieve super-multichannel performance, new high-density multiport Bare Fiber (BF) connectors have been developed for the optical interface of the modules. Unlike conventional optical connectors, the BF connectors do not need a ferrule or spring. This ensures physical contact with excellent insertion loss of less than 0.1 dB for every channel. A polymeric optical waveguide film with a 45/spl deg/ mirror for coupling to the VCSEL/PD arrays by passive optical alignment has also been developed. Also to ensure easy coupling between the VCSEL/PD array chips and the waveguide, a packaging technique has been developed to align and diebond the optical array chips on a substrate. This technique is called Transferred Multichip Bonding (TMB), and can be used to mount optical array chips on a substrate with a positioning error of only several micrometers. These packaging techniques offer the performance of an ultra-parallel interconnection in prototype ParaBIT modules.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128365261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges in packaging a 4 chip FC MCM-L using KGD","authors":"W. Adamjee, C. Corona, J.M. Czamowski, R. Eklund, J. Guajardo, D. Hedges, A. Youngblood","doi":"10.1109/ECTC.1998.678733","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678733","url":null,"abstract":"The FC MCM-L (Flip Chip MultiChip Module on Laminate) product is comprised of four Known Good Die (KGD) on 25/spl times/25 mm laminate substrate with solder clad bond pads. The FC MCM-L package was similar to that of single chip flip chip on laminate product with respect to assembly processing and material set. However, differences related to KGD, and the close proximity of die with minimal substrate real estate provided opportunities for process improvement. This paper describes the manufacturing processes and challenges encountered in the chip attach and underfill encapsulation processes. Finally, the MCM test and reliability results are discussed.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134342824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermo-mechanical analysis of solder joint fatigue and creep in a flip chip on board package subjected to temperature cycling loading","authors":"J. Pang, T. Tan, S. Sitaraman","doi":"10.1109/ECTC.1998.678811","DOIUrl":"https://doi.org/10.1109/ECTC.1998.678811","url":null,"abstract":"Thermo-mechanical stress analysis was conducted on a flip-chip-on-board (FCOB) package with underfill encapsulation. The solder joint fatigue and creep deformation response were modeled for a typical temperature cycling loading of -55 to 125 C. Two temperature cycling loading models with and without the curing part of the temperature history for the encapsulation process were investigated. Two-dimensional plane-strain finite element models of the FCOB package were employed. Elasto-plastic and creep deformation behavior of solder was simulated under the temperature cycling conditions to obtain the stress and strain results. The finite element strain results were used in fatigue life prediction models.","PeriodicalId":422475,"journal":{"name":"1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116039760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}