Three dimensional die surface stress measurements in delaminated and non-delaminated plastic packages

Abstract

In plastic encapsulated electronic packages, mechanical stresses are induced during the encapsulation process. These stresses can cause degraded circuit performance or mechanical failures, and are mainly a result of the uneven expansions and contractions of the various assembly materials that occur due to coefficient of thermal expansion (CTE) mismatches. In this study, special (100) and (111) silicon test chips containing arrays of optimized piezoresistive stress sensor rosettes have been used to characterize die surface stresses in encapsulated packages. The sensors on the (100) test chips were able to accurately measure two in-plane stress components in a temperature compensated manner, while the rosettes on the (111) test chips were uniquely capable of evaluating all the 6 stress components (four in a temperature compensated manner). Calibrated and characterized (100) and (111) test chips were encapsulated in 240 pin quad flat packs (QFP's). The post packaging room temperature resistances of the sensors were then recorded. The stresses on the die surface were calculated using the measured resistance changes and the appropriate theoretical equations. For comparison purposes, three-dimensional nonlinear finite element simulations of the plastic encapsulated packages were also performed. The presence of delaminations between the die surface and the encapsulant was explored using C-mode scanning acoustic microscopy (C-SAM). The potential of the (111) stress test chips for detecting delaminations and for aiding the understanding of stress distributions in delaminated packages has been demonstrated.