Stencil printing process development for low cost flip chip interconnect

Abstract

Traditional methods for forming flip chip interconnection include evaporation and electroplating. While both options have proven performance records, their costs are too high for many of today's cost-sensitive applications. Motorola AISL (Advanced Interconnect Systems Laboratory) developed a low cost flip chip interconnect alternative, which electroless plates Ni/Au as the under bump metallurgy (UBM), deposits solder paste using a stencil or photoresist mask, and reflows the paste to form solder bumps. This paper is focused on the stencil print process development for wafer solder bumping. Solder paste selection, characterization, stencil design, and process parameter optimization are critical factors for successful fine pitch stencil printing. Fine mesh eutectic solder pastes (Type 5: -500+635, Type 6: -635) with different flux vehicles were evaluated for printability and reflow studies. Paste and flux modification and co-development with vendors for this specific application were conducted. An optimal paste, with specified viscosity and desired print, reflow and cleaning behavior, was developed. Wafer stencil design rules were established to deposit the right amount of solder paste to form the required reflowed solder bump height without bridges between pads. Printing and reflow design of experiments were performed to establish the baseline and optimum process parameters. Solder bump characterizations, including bump height and uniformity, composition, shear force, and SEM bump profile and cross section microstructure analysis, were conducted. Development and characterization results are presented.