存储设备的芯片级封装

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206) Pub Date : 1998-05-25 DOI:10.1109/ECTC.1998.678737

Y. Akiyama, A. Nishimura, I. Anjoh

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引用次数: 4

摘要

一种低成本、高可靠性的芯片级封装已经被开发出来。开发的CSP可以应用于DRAM等中心pad型器件和SRAM、Flash等外围pad型器件。可靠性和高产量是芯片规模封装必须克服的主要技术挑战。本文揭示了日立的原始CSP概念，并展示了我们的CSP如何克服这些挑战。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Chip scale packaging for memory devices

A low cost, high reliability chip scale package has been developed for memory devices. The developed CSP can be applied to center pad type devices such as DRAM and to peripheral pad type devices such as SRAM and Flash. Reliability and high volume productivity are the main technological challenges that have to be overcome for chip scale packaging. This paper unveils Hitachi's original CSP concept and shows how our CSP overcomes these challenges.

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来源期刊

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)

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