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Anomalous Spectral Shape Evolution of Ge Raman Shift in Oxidation of SiGe SiGe氧化过程中锗拉曼位移的反常光谱形状演化
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-07-26 DOI: 10.1109/EDTM.2018.8421461
Y. Noma, W. Song, T. Nishimura, T. Yajima, A. Toriumi
{"title":"Anomalous Spectral Shape Evolution of Ge Raman Shift in Oxidation of SiGe","authors":"Y. Noma, W. Song, T. Nishimura, T. Yajima, A. Toriumi","doi":"10.1109/EDTM.2018.8421461","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421461","url":null,"abstract":"This paper reports anomalous Raman peak shape of Ge in SiGe oxidation. The results in Raman spectroscopy in SiGe suggest that Ge precipitation occurs at the SiGe interface associated with the oxidation. Non-oxidized Ge remaining at the interface should be related to the interface degradation which should lead to poor gate stack properties. Finally, it discusses how to achieve well-behaved SiGe gate stacks by considering anomalous Raman spectrum in the oxidation.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116370344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermoelectric Characteristics of Rapid-Melting-Grown SiGe Wires Measured by Peltier Cooling Experiment 用Peltier冷却实验测量了快速熔化生长SiGe导线的热电特性
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-07-26 DOI: 10.1109/EDTM.2018.8421517
S. Hashimoto, Kouta Takahashi, S. Oba, T. Terada, Masataka Ogasawara, M. Tomita, M. Kurosawa, Takanobu Watanabe
{"title":"Thermoelectric Characteristics of Rapid-Melting-Grown SiGe Wires Measured by Peltier Cooling Experiment","authors":"S. Hashimoto, Kouta Takahashi, S. Oba, T. Terada, Masataka Ogasawara, M. Tomita, M. Kurosawa, Takanobu Watanabe","doi":"10.1109/EDTM.2018.8421517","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421517","url":null,"abstract":"We performed a Peltier cooling experiment using SiGe wires fabricated by rapid-melting-growth (RMG) method. Thermal conductivity κ of SiGe wires estimated from the Peltier heating/cooling rate showed a significant dependence on the RMG process; the growth into one direction from a Si seed island exhibit a smaller κ than the bilateral growth. According to molecular dynamics simulation, the κ hardly depend on the compositional distribution, indicating the impact of the difference in the RMG processes.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124658311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ferroelectric Characteristics of Ultra-thin Hf1-xZrxO2 Gate Stack and 1T Memory Operation Applications 超薄Hf1-xZrxO2栅极堆栈的铁电特性及1T存储操作应用
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-07-26 DOI: 10.1109/EDTM.2018.8421475
M. H. Lee, C. Kuo, C.-H. Tang, H. Chen, C.-Y. Liao, R. Hong, S. Gu, Y.-C. Chou, Z. Wang, Syuan-Ye Chen, P. Chen, M. Liao, K.-S. Li
{"title":"Ferroelectric Characteristics of Ultra-thin Hf1-xZrxO2 Gate Stack and 1T Memory Operation Applications","authors":"M. H. Lee, C. Kuo, C.-H. Tang, H. Chen, C.-Y. Liao, R. Hong, S. Gu, Y.-C. Chou, Z. Wang, Syuan-Ye Chen, P. Chen, M. Liao, K.-S. Li","doi":"10.1109/EDTM.2018.8421475","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421475","url":null,"abstract":"The typical characteristics of ultra-thin Zr doped in HfO<inf>2</inf> as gate stack is demonstrated. The 1T memory window of P/E retention is 0.67V for 5nm and 1.52V for 7nm after extrapolated 10 years with V<inf>P</inf>/E=± 4.8V, and >10<sup>9</sup> cycles of read endurance. It is promising to use ultra-thin FE-HZO as the guidelines for 1T memory applications.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
2D Materials for Ubiquitous Electronics 泛在电子的二维材料
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421456
Saptarshi Das
{"title":"2D Materials for Ubiquitous Electronics","authors":"Saptarshi Das","doi":"10.1109/EDTM.2018.8421456","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421456","url":null,"abstract":"The interest in two dimensional (2D) materials is rapidly spreading across all scientific and engineering disciplines due to their exquisite physical properties which not only provides a platform to investigate new and intriguing phenomena but also promises solutions to many imminent technological challenges. With the emergence of the era of Internet of Things (IoT), the 2D layered materials like graphene, MoS2, WSe2, Black Phosphorus, and many more are finding their widespread applications in conventional electronics, flexible electronics, straintronics, self-powered electronics, optoelectronics and even in brain inspired electronics. Low cost and high yield synthesis of pristine quality of these 2D materials is critical towards their commercial implementation. In my talk, I will provide a holistic understanding of 2D materials starting from a novel electrochemical method of synthesizing monolayers of various 2D materials to their eventual ubiquitous applications in various branches of electronics [1]–[20].","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123891098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy and Area Efficient Tunnel FET-based Spiking Neural Networks 基于能量和面积高效隧道场效应的脉冲神经网络
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421527
Dinesh Rajasekharan, S. S. Chauhan, A. Trivedi, Y. Chauhan
{"title":"Energy and Area Efficient Tunnel FET-based Spiking Neural Networks","authors":"Dinesh Rajasekharan, S. S. Chauhan, A. Trivedi, Y. Chauhan","doi":"10.1109/EDTM.2018.8421527","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421527","url":null,"abstract":"Exploiting the Tunnel FET (TFET) properties such as unidirectional conduction and asymmetric drain and source, we propose for the first time a novel TFET-based circuit design mechanism for spike timing dependent plasticity process. In the proposed circuit, we are able to reduce the transistor count by half, making the circuit more area and energy efficient. A neuron receiving input from ten synapses, containing the proposed learning circuit, was simulated and it operated with reduced area and energy consumption compared to the MOSFET-based implementation.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132233267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Evolution of Panel Level Packaging 面板级封装的演变
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421523
R. Aschenbrenner, M. Töpper, T. Braun, A. Ostmann
{"title":"The Evolution of Panel Level Packaging","authors":"R. Aschenbrenner, M. Töpper, T. Braun, A. Ostmann","doi":"10.1109/EDTM.2018.8421523","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421523","url":null,"abstract":"Developing demands and the market show two main trends helping to shape the ongoing development of system integration technologies. First of all is an ongoing increase in the number of functions directly included in a system — such as electrical, optical, mechanical, biological and chemical processes — combined with the demand for higher reliability and longer system lifetime. Second is the increasingly seamless merging of products and electronics, which necessitates adapting electronics to predefined materials, forms and application environments. Only by these means systems sensors — which are often installed in extremely harsh environments — and signal processing can be implemented near to the point where signals are occurring. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. Both technologies are under the frame of Panel Level Packaging research at Fraunhofer I ZM. This paper describes the potential of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers with an outlook of advanced large area encapsulation processes for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131141760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation 考虑线边粗糙度和功函数变化的负电容UTB SOI mosfet分析
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421472
P. Chiu, V. Hu
{"title":"Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation","authors":"P. Chiu, V. Hu","doi":"10.1109/EDTM.2018.8421472","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421472","url":null,"abstract":"We analyze the threshold voltage (Vt) and switching time (ST) variations of negative capacitance UTB SOI MOSFETs (NC-SOI) and UTB SOI MOSFETs considering line-edge roughness (LER) and work function variation (WFV). Compared to SOI, NC-SOI exhibits smaller LER induced Vt variations (σVt}) and comparable WFV induced Vt variations. LER induced σVt} can be suppressed by negative capacitance, while WFV induced σVt} cannot be suppressed by negative capacitance. For considering LER, NC-SOI with larger subthreshold swing (SS) and worse short channel effect exhibits better capacitance matching, larger voltage gain (Av), and larger threshold voltage difference (VtNC-SOI-VtSOI), which mitigates the σVt}. For NC-SOI MOSFETs, WFV induced σVt} (=16.2mV) is larger than LER induced σVt} (=3.8mV). For SOI MOSFETs, WFV and LER show comparable σVt}. However, for both NC-SOI and SOI MOSFETs, LER induced ST variations are larger than the WFV induced ST variations. This is because transition charge (Δ Q}) and effective drive current (Ieff) are positively correlated for considering WFV and negatively correlated for considering LER. Compared with SOI, NC-SOI considering LER and WFV exhibits smaller ST variations due to larger Ieff.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Consistent Predictive Simulation of SRAM-Cell Performance Degradation Including Both MOSFET Fabrication Variation and Aging sram电池性能退化的一致性预测模拟，包括MOSFET制造变化和老化
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421499
Hiroaki Gau, Nezam Rohbani, T. Maiti, D. Navarro, M. Miura-Mattausch, H. Mattausch, H. Takatsuka
{"title":"Consistent Predictive Simulation of SRAM-Cell Performance Degradation Including Both MOSFET Fabrication Variation and Aging","authors":"Hiroaki Gau, Nezam Rohbani, T. Maiti, D. Navarro, M. Miura-Mattausch, H. Mattausch, H. Takatsuka","doi":"10.1109/EDTM.2018.8421499","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421499","url":null,"abstract":"We have developed a methodology to simulate circuit aging including the device fabrication variation with less simulation effort. As an example a 6T SRAM cell has been investigated. It is demonstrated that the variability range of the circuit performance is further enhanced due to the long-term device aging. Among the device parameters, the impurity concentration variation plays a particularly important role for the circuit performance variation. However, most sensitive for the aging degradation is the channel-length variation, because it increases the aging effect drastically. Further, the individual aging of each MOSFET is strongly dependent on the actual stress during circuit operation.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132077991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Technology Innovations in Selective ALD for Next-Generation Contacts and Vias 下一代触点和过孔选择性ALD的技术创新
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421521
S. Datta, A. Kummel
{"title":"Technology Innovations in Selective ALD for Next-Generation Contacts and Vias","authors":"S. Datta, A. Kummel","doi":"10.1109/EDTM.2018.8421521","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421521","url":null,"abstract":"Monolithic 3D integrated circuits with vertically stacked transistors and memory cells results in shorter wires, thereby mitigating wire-related energy and delay problems. However, new fabrication techniques need to be developed that address the challenge of filling high aspect ratio vertical trenches with ultra-low resistivity conductors and barrier (or no barrier) to enable fine grained stacking at the gate level. In this invited lecture, we describe progress in two key process capabilities such as selective ALD of metal silicide and nanofog sealing of low-k dielectric that enable creation of high density vias.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131698332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Anisotropic thermal conductivity of vertically self-ordered Nanocrystalline Boron Nitride thin films for thermal hotspot mitigation in electronics 垂直自有序纳米氮化硼薄膜的各向异性热导率及其在电子学中的热热点缓解
2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM) Pub Date : 2018-03-13 DOI: 10.1109/EDTM.2018.8421414
S. H. Tsang, Olivier Cometto, M. K. Samani, Shuangxi Sun, Johan Liu, Edwin Hang Tong Teo
{"title":"Anisotropic thermal conductivity of vertically self-ordered Nanocrystalline Boron Nitride thin films for thermal hotspot mitigation in electronics","authors":"S. H. Tsang, Olivier Cometto, M. K. Samani, Shuangxi Sun, Johan Liu, Edwin Hang Tong Teo","doi":"10.1109/EDTM.2018.8421414","DOIUrl":"https://doi.org/10.1109/EDTM.2018.8421414","url":null,"abstract":"Thermal-crosstalk has become a prominent issue in modern electronic. Here, we present a new type of vertically-ordered Boron Nitride (voBN) thin films to address such limitation. voBN has a high anisotropic thermal conductivity with 16 times difference between through-plane and in-plane and can be deposited in room temperature. We studied the thermal properties with 3omega method and verified with COMSOL Multiphysics simulations. Such characteristic would allow hotspot density to increase by 295%.","PeriodicalId":418495,"journal":{"name":"2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM)","volume":"375 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120941177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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