Technology Innovations in Selective ALD for Next-Generation Contacts and Vias

Abstract

Monolithic 3D integrated circuits with vertically stacked transistors and memory cells results in shorter wires, thereby mitigating wire-related energy and delay problems. However, new fabrication techniques need to be developed that address the challenge of filling high aspect ratio vertical trenches with ultra-low resistivity conductors and barrier (or no barrier) to enable fine grained stacking at the gate level. In this invited lecture, we describe progress in two key process capabilities such as selective ALD of metal silicide and nanofog sealing of low-k dielectric that enable creation of high density vias.