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Growth of semi-polar (101̄3) AlN films on the silicon 硅表面生长半极性(101)AlN薄膜
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669191
Shih-Bin Jhong, Maw-Shung Lee, Sean Wu, Kuan-Ting Liu, Zhi-Xun Lin, Y. Lai, Ping-Feng Yang
{"title":"Growth of semi-polar (101̄3) AlN films on the silicon","authors":"Shih-Bin Jhong, Maw-Shung Lee, Sean Wu, Kuan-Ting Liu, Zhi-Xun Lin, Y. Lai, Ping-Feng Yang","doi":"10.1109/ISNE.2010.5669191","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669191","url":null,"abstract":"Highly semi-polar (101̄3) oriented and fine structural AlN films were successfully prepared on silicon substrate by rf magnetron sputtering in this research. The dependence of the nitrogen concentrations and the material characteristics of the films (crystalline structure and micro morphology) were investigated. The crystalline structure of the films was determined by X-ray diffraction (XRD) and the surface microstructure of films was quantitatively investigated using an atomic force microscope (AFM). Different nitrogen concentrations (50%, 58%, 67% and 75%) were used to deposit the films. As decreasing the nitrogen concentrations, the XRD intensity of the semi-polar (101̄3) oriented increases, the crystallite size of the films increases and the roughness of top surface decreases. The experimental results demonstrate that the highly semi-polar (101̄3) oriented AlN films appeared at the lower nitrogen concentration.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125467378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ELFR experiment test verifying anomaly of nano-DRAM products in W-plug process ELFR实验验证了纳米dram产品在W-plug工艺中的异常
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669148
Chiao-Lo Chiang, Mu-Chun Wang, Yu-Min Chung, Chung-Ming Chu, Shou-Kong Fan, Chin-Chia Kuo, I-Shan Yen
{"title":"ELFR experiment test verifying anomaly of nano-DRAM products in W-plug process","authors":"Chiao-Lo Chiang, Mu-Chun Wang, Yu-Min Chung, Chung-Ming Chu, Shou-Kong Fan, Chin-Chia Kuo, I-Shan Yen","doi":"10.1109/ISNE.2010.5669148","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669148","url":null,"abstract":"Early-life failure-rate (ELFR) test is a useful gauge to screen out the harmful or latent-defect memory products. In nano-regime, this test is still suitable to be applied on these kinds of memory products. Through this reliability test, some gap-filling quality with W-plug in via or contact structure is not compact well, causing the degradation in electrical characteristics and deteriorating the function operation with Shmoo function tester. Using the failure analysis skill, this failure mode was located and identified.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122041956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Enhanced exciton-phonon efficiency in photoluminescence of SrTiO3 :Er films covered on ZnO nanorods ZnO纳米棒覆盖的SrTiO3:Er薄膜在光致发光中的激子-声子效率提高
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669167
Shean-Yih Lee, Shich-Chuan Wu, P. Yang
{"title":"Enhanced exciton-phonon efficiency in photoluminescence of SrTiO3 :Er films covered on ZnO nanorods","authors":"Shean-Yih Lee, Shich-Chuan Wu, P. Yang","doi":"10.1109/ISNE.2010.5669167","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669167","url":null,"abstract":"Characteristics of light emission of Er-doped SrTiO3 (STO) thin films (STO : Er) deposited on different surface morphologies by a sputtering technique were investigated. The luminescence efficiency of Er-doped STO films covered on ZnO nanorods was greater than deposited directly on Si (100) substrates in all specimens. Formation of one-dimensional well-aligned ZnO nanorods has been achieved using a simple aqueous solution method at low temperatures. The dependence of luminescence efficiency on Er3+ concentrations and annealing temperatures in the Er-doped STO films is governed by crystallinity and ion-ion interaction. The photoluminescence (PL) measurement of the Er-doped STO films covered on ZnO nanorods show that the much stronger intensity of green light is observed at annealing temperature 700 °C and 3 mol% Er3+ -doped concentration. The presence of clusters as the Er concentration exceed 3 mol% will diminish the emission intensity. Besides, concentration quenching was observed on STO films containing 5 mol% Er dopant. The phenomenon was attributed to energy transference and cross relaxation between closely sited Er3+ ions in the STO lattice. We also showed that the quenching mechanism of the luminescent intensity is evidently relational with Er-doped concentrations and annealing temperatures. The photoluminescence properties suggest that adding a 3 mol% Er-doped STO films covered on ZnO nanorods is the optimal choice for optoelectronic device applications.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125753991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The etching and annealing influences of front-contact ZnO:Ga on amorphous thin film silicon solar cells 前接触ZnO:Ga对非晶硅薄膜太阳电池的腐蚀和退火影响
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669201
Hung-Jen Yang, Chien-Liang Wu, Chian-fu Huang, Chun-Heng Chen, Yi-Chan Chen, Wen-Cheng Lee
{"title":"The etching and annealing influences of front-contact ZnO:Ga on amorphous thin film silicon solar cells","authors":"Hung-Jen Yang, Chien-Liang Wu, Chian-fu Huang, Chun-Heng Chen, Yi-Chan Chen, Wen-Cheng Lee","doi":"10.1109/ISNE.2010.5669201","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669201","url":null,"abstract":"For achieving higher performance of amorphous silicon thin film solar cell, the front-contact ZnO:Al is needed to be concerned. In this paper, we focus on how the front contact ZnO:Al influences the a-Si:H thin film solar cell. In order to understand the relationship between the front-contact ZnO:Al and device, we establish a model to simulate how the feature size of the textured ZnO:Al influence the haze and short-circuit current. Moreover we introduce the anneal effect on a-Si:H thin film solar cell.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130044258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of floating-point CORDIC rotation and vectoring based on look up tables and multipliers 基于查找表和乘法器的浮点CORDIC旋转和矢量实现
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669143
Shen-Fu Hsiao, Chia-Shen Wen, Hsin-Mau Lee
{"title":"Implementation of floating-point CORDIC rotation and vectoring based on look up tables and multipliers","authors":"Shen-Fu Hsiao, Chia-Shen Wen, Hsin-Mau Lee","doi":"10.1109/ISNE.2010.5669143","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669143","url":null,"abstract":"A unified design is presented that can execute floating-point CORDIC operations in both rotation and vectoring modes with significantly reduced computation latency. Unlike previous pipelined CORDIC implementations usually requiring a sequence of micro-rotation stages proportional to bit accuracy, the proposed design consists of only two stages, coarse and fine stages, with each stage realized using ROM, adders, and multipliers. The bit-widths of the composing hardware components are also optimized to minimize the cost while maintaining the computation accuracy. The proposed design can be applied to applications that require high-precision arithmetic operations with large data representation ranges, such as 3D graphics acceleration.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130977102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A subthreshold SRAM cell with autonomous bitline-voltage clamping 具有自动位线电压箝位的亚阈值SRAM单元
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669177
S. Luo, L. Chiou
{"title":"A subthreshold SRAM cell with autonomous bitline-voltage clamping","authors":"S. Luo, L. Chiou","doi":"10.1109/ISNE.2010.5669177","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669177","url":null,"abstract":"Ultra-low power SRAM is a promising memory for the next-generation electronics that focus on green and power-aware computing. Unfortunately, ultra-low power SRAM encounters serious timing uncertainty. One of the major problems is that the conventional voltage-clamping circuits cannot work when the bitlines have serious with-in-die variations. The full swing, usually required on the bitline, causes unwanted power dispassion. Therefore, this work proposes a novel SRAM cell that can clamp the bitline voltage autonomously. This voltage clamping is also independent in each bitline and is adapted automatically under dynamic voltage scaling. The dynamic power on bitline discharge can be saved by 75% by using the proposed structure, with an acceptable overhead in access time.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115443372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization for novel non-traditional CMOS inverter composed of a junctionless NMOSFET and a gated N+-N−-P transistor 由无结NMOSFET和门控N+-N−-P晶体管组成的新型非传统CMOS逆变器的特性
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669150
Kuan-Yu Lu, Jyi-Tsong Lin, Hsuan-Hsu Chen, Y. Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, Yi-Hsuan Fan
{"title":"Characterization for novel non-traditional CMOS inverter composed of a junctionless NMOSFET and a gated N+-N−-P transistor","authors":"Kuan-Yu Lu, Jyi-Tsong Lin, Hsuan-Hsu Chen, Y. Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, Yi-Hsuan Fan","doi":"10.1109/ISNE.2010.5669150","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669150","url":null,"abstract":"We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N<sup>+</sup>-N<sup>−</sup>-P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N<sup>+</sup>-N<sup>−</sup>-P transistor serves as load, respectively. Based on the measurement date of the N<sup>+</sup>-N<sup>−</sup>-P transistor published, we draw the load line of the non-traditional CMOS inverter and we found out that the N<sup>+</sup>-N<sup>−</sup>-P transistor can be used in the COMS circuit to advance the issues of the conventional CMOS today. Besides, the area reduced more than 46.1% are also be achieved.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123970487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process 亚100纳米CMOS工艺中布局拾音器对MOS晶体管ESD稳健性的影响
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669188
M. Ker, Yong-Ru Wen, Wen-Yi Chen, Chun-Yu Lin
{"title":"Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process","authors":"M. Ker, Yong-Ru Wen, Wen-Yi Chen, Chun-Yu Lin","doi":"10.1109/ISNE.2010.5669188","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669188","url":null,"abstract":"Electrostatic discharge (ESD) is an inevitable event in CMOS integrated circuits. Layout structure is one of the important factors that affect ESD robustness of MOS transistors. In this work, the impact of inserting additional layout pickups to ESD robustness of both multi-finger NMOS and PMOS transistors has been studied in a 90-nm CMOS process. Measurement results have shown that multi-finger MOS transistors without additional pickup inserted into their source regions can sustain a higher ESD protection level at the same effective device dimension.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127971856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication CESL沉积促进45纳米节点工艺制造n/p mosfet
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669140
Mu-Chun Wang, Hsin-Chia Yang, W. Liao, Hsiu-Yen Yang, Yao-Yuan Hoe, K. Lin, Shuang-Yuan Chen
{"title":"CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication","authors":"Mu-Chun Wang, Hsin-Chia Yang, W. Liao, Hsiu-Yen Yang, Yao-Yuan Hoe, K. Lin, Shuang-Yuan Chen","doi":"10.1109/ISNE.2010.5669140","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669140","url":null,"abstract":"In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This phenomenon is obviously observed with devices, width/length=W/L= 10/10 and 10/.08 (µm/µm). Moreover, the trend evidence for tensile strain benefited to nMOSFETs and pMOSFETs, but for compressive strain favoring pMOSFTEs and not hugely degrading nMOSFETs, is also achieved.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122281421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of high-throughput re-encoder for soft-decision Reed-Solomon decoding 软判决Reed-Solomon译码的高吞吐量重编码器设计
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669141
Y. Lu, Ming-Der Shieh
{"title":"Design of high-throughput re-encoder for soft-decision Reed-Solomon decoding","authors":"Y. Lu, Ming-Der Shieh","doi":"10.1109/ISNE.2010.5669141","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669141","url":null,"abstract":"The re-encoding and coordinate transformation techniques are usually employed to reduce the computational complexity of interpolation, which is the most computation-intensive step in the algebraic soft-decision decoding of Reed-Solomon (RS) codes. In this paper, we present a high-throughput re-encoder design for soft-decision decoding a (255, 239) RS code. With the developed scheduling scheme and a folding architecture, the resulting design can significantly shorten the latency of the re-encoding process to achieve a high throughput rate and effectively reduce the hardware requirement of the re-encoder. Compared to related work, the developed re-encoder has a 4-fold increase in the throughput rate with only 16% hardware overhead.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133438409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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