{"title":"软判决Reed-Solomon译码的高吞吐量重编码器设计","authors":"Y. Lu, Ming-Der Shieh","doi":"10.1109/ISNE.2010.5669141","DOIUrl":null,"url":null,"abstract":"The re-encoding and coordinate transformation techniques are usually employed to reduce the computational complexity of interpolation, which is the most computation-intensive step in the algebraic soft-decision decoding of Reed-Solomon (RS) codes. In this paper, we present a high-throughput re-encoder design for soft-decision decoding a (255, 239) RS code. With the developed scheduling scheme and a folding architecture, the resulting design can significantly shorten the latency of the re-encoding process to achieve a high throughput rate and effectively reduce the hardware requirement of the re-encoder. Compared to related work, the developed re-encoder has a 4-fold increase in the throughput rate with only 16% hardware overhead.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of high-throughput re-encoder for soft-decision Reed-Solomon decoding\",\"authors\":\"Y. Lu, Ming-Der Shieh\",\"doi\":\"10.1109/ISNE.2010.5669141\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The re-encoding and coordinate transformation techniques are usually employed to reduce the computational complexity of interpolation, which is the most computation-intensive step in the algebraic soft-decision decoding of Reed-Solomon (RS) codes. In this paper, we present a high-throughput re-encoder design for soft-decision decoding a (255, 239) RS code. With the developed scheduling scheme and a folding architecture, the resulting design can significantly shorten the latency of the re-encoding process to achieve a high throughput rate and effectively reduce the hardware requirement of the re-encoder. Compared to related work, the developed re-encoder has a 4-fold increase in the throughput rate with only 16% hardware overhead.\",\"PeriodicalId\":412093,\"journal\":{\"name\":\"2010 International Symposium on Next Generation Electronics\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-12-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International Symposium on Next Generation Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISNE.2010.5669141\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Symposium on Next Generation Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2010.5669141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of high-throughput re-encoder for soft-decision Reed-Solomon decoding
The re-encoding and coordinate transformation techniques are usually employed to reduce the computational complexity of interpolation, which is the most computation-intensive step in the algebraic soft-decision decoding of Reed-Solomon (RS) codes. In this paper, we present a high-throughput re-encoder design for soft-decision decoding a (255, 239) RS code. With the developed scheduling scheme and a folding architecture, the resulting design can significantly shorten the latency of the re-encoding process to achieve a high throughput rate and effectively reduce the hardware requirement of the re-encoder. Compared to related work, the developed re-encoder has a 4-fold increase in the throughput rate with only 16% hardware overhead.