CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication

Mu-Chun Wang, Hsin-Chia Yang, W. Liao, Hsiu-Yen Yang, Yao-Yuan Hoe, K. Lin, Shuang-Yuan Chen
{"title":"CESL deposition promoting n/p MOSFETs under 45-nm-node process fabrication","authors":"Mu-Chun Wang, Hsin-Chia Yang, W. Liao, Hsiu-Yen Yang, Yao-Yuan Hoe, K. Lin, Shuang-Yuan Chen","doi":"10.1109/ISNE.2010.5669140","DOIUrl":null,"url":null,"abstract":"In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This phenomenon is obviously observed with devices, width/length=W/L= 10/10 and 10/.08 (µm/µm). Moreover, the trend evidence for tensile strain benefited to nMOSFETs and pMOSFETs, but for compressive strain favoring pMOSFTEs and not hugely degrading nMOSFETs, is also achieved.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Symposium on Next Generation Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2010.5669140","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In this study, the process technology of contact-etching stop-layer (CESL) with LPCVD or PECVD is performed by interlayer-dielectric-SiNx stressing layer to form the tensile or compressive strained n/p MOSFETs. Because the strain effect on MOSFET devices is finite, the promoting performance of source/drain current is increased more while the channel lengths of the devices are decreased more. This phenomenon is obviously observed with devices, width/length=W/L= 10/10 and 10/.08 (µm/µm). Moreover, the trend evidence for tensile strain benefited to nMOSFETs and pMOSFETs, but for compressive strain favoring pMOSFTEs and not hugely degrading nMOSFETs, is also achieved.
CESL沉积促进45纳米节点工艺制造n/p mosfet
在本研究中,采用LPCVD或PECVD的接触刻蚀停止层(CESL)工艺,通过层间-介电- sinx应力层形成拉伸或压缩应变n/p的mosfet。由于应变对MOSFET器件的影响是有限的,因此源漏电流的促进性能越高,器件的沟道长度越短。当宽度/长度=W/L= 10/10和10/ 0.08时,可以明显观察到这种现象(µm /µm)。此外,还获得了拉伸应变有利于nmosfet和pmosfet的趋势证据,但压缩应变有利于pmosfte而不会大大降低nmosfet。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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