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2010 International Symposium on Next Generation Electronics最新文献

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Enhancement of light harvesting in dye-sensitized solar cells with TiCl4 treatment and high-reflective Pt/FTO/Al counterelectrode 用TiCl4处理和高反射Pt/FTO/Al对电极增强染料敏化太阳能电池的光收集
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669198
Yung-Chun Wu, Bo-Yu Lai, Chien-ting Chen, Shihang Yang, Shin Cheng
{"title":"Enhancement of light harvesting in dye-sensitized solar cells with TiCl4 treatment and high-reflective Pt/FTO/Al counterelectrode","authors":"Yung-Chun Wu, Bo-Yu Lai, Chien-ting Chen, Shihang Yang, Shin Cheng","doi":"10.1109/ISNE.2010.5669198","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669198","url":null,"abstract":"This study attempts to enhance the performance of dye-sensitized solar cells (DSSCs) by integrating the TiCl4 treatment on porous TiO2 and a novel high-reflective counter electrode, Pt/FTO/Al. Experimental results indicate that light scattered by TiCl4-treated large TiO2 particle sizes and light reflected by the counter electrode decrease the total transmission of the modified cell. Additionally, the modified DSSCs significantly increase the short-circuit photocurrent density (Jsc) by about 34% higher than that of the standard (STD) cell, resulting in a 5.62% energy conversion efficiency (η), i.e. about 42% higher than that of a standard cell. Moreover, incident monochromatic photon-to-current conversion efficiency (IPCE) spectra of the modified DSSCs reveal a higher value than that of a standard cell, especially in the higher wavelength range.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121421811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
To achieve a novel weak snapback characteristic in the high voltage nLDMOS 在高压nLDMOS中实现了一种新的弱回调特性
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669169
Shen-Li Chen, T. Wu, Hung-Wei Chen, C. Shih, Po-Ying Chen
{"title":"To achieve a novel weak snapback characteristic in the high voltage nLDMOS","authors":"Shen-Li Chen, T. Wu, Hung-Wei Chen, C. Shih, Po-Ying Chen","doi":"10.1109/ISNE.2010.5669169","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669169","url":null,"abstract":"A drain-side engineering to LDMOS by doping concentration and length modulations of the N-type adaptive layer to obtain weak snapback characteristic nLDMOS are presented in this work. It's a novel method to reduce trigger voltage(Vt1) and to increase holding voltage(Vh). These efforts will be very suitable for the HV power management IC applications. Meanwhile, in this work, we will discuss trigger voltage, holding voltage and Ron resistance distribution of these novel HV nLDMOS devices.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131001477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A CMOS optical receiver for optoelectronic integrated circuits 一种用于光电集成电路的CMOS光接收器
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669185
R. Y. Chen, Zong-Yi Yang, Ming-Jen Chang
{"title":"A CMOS optical receiver for optoelectronic integrated circuits","authors":"R. Y. Chen, Zong-Yi Yang, Ming-Jen Chang","doi":"10.1109/ISNE.2010.5669185","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669185","url":null,"abstract":"A CMOS receiver for optical wireless communication is presented. A stable feedback transimpedance amplifier (TIA) is designed adopting a current-mode amplifier as its feedforward gain element. A band-pass limiting amplifier is employed to boost the outputs of the receiver front-end. Implemented in a 0.35um CMOS, the optical wireless receiver achieves a maximum transimpedance gain of 95.9 dBΩ. The maximum bandwidth is 220 MHz in the presence of a 5pF photodiode capacitance.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122762193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of nano-regime strained MOSFETs with temperature effects 温度效应下纳米应变mosfet的研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669166
Hsin-Chia Yang, W. Liao, M. Peng, Mu-Chun Wang, Z. Hsieh, Shuang-Yuan Chen, Heng-Sheng Huang
{"title":"Study of nano-regime strained MOSFETs with temperature effects","authors":"Hsin-Chia Yang, W. Liao, M. Peng, Mu-Chun Wang, Z. Hsieh, Shuang-Yuan Chen, Heng-Sheng Huang","doi":"10.1109/ISNE.2010.5669166","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669166","url":null,"abstract":"Strained engineering in nano process technology is considered to be a promising enhancements on the electric characteristics of MOSFET devices. Both tensile and compressive strains are applied to NMOS and PMOS individually using silicon nitride as contact etching stop layer (CESL). As appeared in this study, the electrical characteristics are to be compared with or without strain on 10µm/10µm (channel length/ width) at various temperatures, and more benefits of compressive CESL and tensile CESL for NMOS and PMOS, respectively, are seen. One thus goes on to check with the trans-conductance (gm) and the leakage current. The data that were shown assure us the next-generation promising devices.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128461633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A highly linear multiple-gated CMOS downconverter using parallel resonators for low supply voltage 一种采用并联谐振器的高线性多门控CMOS下变频器
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669171
J. Wu, C. Yeh, C. Liou, Y. Guo
{"title":"A highly linear multiple-gated CMOS downconverter using parallel resonators for low supply voltage","authors":"J. Wu, C. Yeh, C. Liou, Y. Guo","doi":"10.1109/ISNE.2010.5669171","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669171","url":null,"abstract":"A low-voltage and high-linearity downconverter RFIC design using TSMC 0.18 µm CMOS foundry for WiMAX applications is presented in this paper. The LC resonator is used to block DC and RF signals for low supply voltage and the multiple-gated CMOS is adopted to eliminate third-order nonlinear term for high linearity. The crucial simulated results of WiMAX downconverter include that a conversion gain is 5.3 dB, an input 1 dB compression point (IP1dB) is −9 dBm, an input third-order intercept point (IIP3) is 1 dBm, and a noise figure (NF) is 12.2 dB. The supply voltage of 0.8 V is used and the power consumption is equal to 8 mW.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128573166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study of carbon nanotube pillar arrays' edge effect on field emission characteristics 碳纳米管柱阵列边缘效应对场发射特性的影响研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669164
C. Juan, Jun-Han Lin
{"title":"Study of carbon nanotube pillar arrays' edge effect on field emission characteristics","authors":"C. Juan, Jun-Han Lin","doi":"10.1109/ISNE.2010.5669164","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669164","url":null,"abstract":"Effect of carbon nanotube pillar arrays' edge effect on field emission characteristics is first studied. The ratio of field emission current density at 5.733V/µm is about 55∶ 6.5∶ 1 which is nearly proportional to the edge ratio (50∶5∶1) for small, middle, and large sizes of CNTs' arrays. Besides, ultra low turn-on field (∼1.4 V/µm), well emission image uniformity and stability of about ±6.52 % at 650V were also achieved.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115885912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel vertical MOSFET with bMPI structure for 1T-DRAM application 一种适用于1T-DRAM的bMPI结构的新型垂直MOSFET
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1080/10584587.2011.576903
Cheng-Hsin Chen, Jyi-Tsong Lin, Y. Eng, Po-Hsieh Lin, Hsien-Nan Chiu, Tzu-Feng Chang, Chih-Hsuan Tai, Kuan-Yu Lu, Yi-Hsuan Fan, Yu-Che Chang, Hsuan-Hsu Chen
{"title":"A novel vertical MOSFET with bMPI structure for 1T-DRAM application","authors":"Cheng-Hsin Chen, Jyi-Tsong Lin, Y. Eng, Po-Hsieh Lin, Hsien-Nan Chiu, Tzu-Feng Chang, Chih-Hsuan Tai, Kuan-Yu Lu, Yi-Hsuan Fan, Yu-Che Chang, Hsuan-Hsu Chen","doi":"10.1080/10584587.2011.576903","DOIUrl":"https://doi.org/10.1080/10584587.2011.576903","url":null,"abstract":"This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114535483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-throughput de-blocking filter accelerator for high-resolution H.264/AVC/SVC decoding 用于高分辨率H.264/AVC/SVC解码的高通量去阻塞滤波器加速器
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669161
Cheng-Hao Chen, Chih-Hao Chang, Kuan-Hung Chen
{"title":"High-throughput de-blocking filter accelerator for high-resolution H.264/AVC/SVC decoding","authors":"Cheng-Hao Chen, Chih-Hao Chang, Kuan-Hung Chen","doi":"10.1109/ISNE.2010.5669161","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669161","url":null,"abstract":"This paper presents a high-throughput deblocking filter accelerator which can process one macro block (MB) within 48 cycles for H.264/AVC/SVC. This innovation is achieved by considering both luminance and chrominance data together in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously execute filtering of four edges. Besides, interleaved memory organization is adopted to eliminate all the data conflicts. This design keeps the input/output data order compliant with the raster scanning order so that no additional interfacing overhead is required for reordering the primary input and output data. After being implemented by using a 0.18-µm CMOS technology, this work can achieve the real-time performance requirement of 6K (6000 × 4000@30fps) format when operated at 135 MHz frequency at the cost of 41.6k gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also possesses higher hardware computing efficiency.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115115716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A numerical study of RF performance for a junctionless vertical MOSFET 无结垂直MOSFET射频性能的数值研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669162
Chih-Hsuan Tai, Jyi-Tsong Lin, Y. Eng, Kuan-Yu Lu, Cheng-Hsin Chen, Yu-Che Chang, Yi-Hsuan Fan
{"title":"A numerical study of RF performance for a junctionless vertical MOSFET","authors":"Chih-Hsuan Tai, Jyi-Tsong Lin, Y. Eng, Kuan-Yu Lu, Cheng-Hsin Chen, Yu-Che Chang, Yi-Hsuan Fan","doi":"10.1109/ISNE.2010.5669162","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669162","url":null,"abstract":"In this paper, for the first time, we demonstrate the radio frequency (RF) performance of a junctionless vertical MOSFET (JLVMOS). According to the numerical simulation results, the JLVMOS can obtain higher gm, lower gd, in comparison to a junctionless planar SOI MOSFET. This because the vertical double-gate (DG) scheme truly helps to increase the gate controllability over the channel region, resulting in reduced short-channel effects (SCEs).","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133638068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Application of multi-wall carbon nanotube/SiC composite to thermal dissipation of high-bright light emitting diode 多壁碳纳米管/碳化硅复合材料在高亮度发光二极管散热中的应用
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669200
Bing-Jing Li, Chih-Hsiang Chang, Y. Su, K. Gan, Jianghui Hong
{"title":"Application of multi-wall carbon nanotube/SiC composite to thermal dissipation of high-bright light emitting diode","authors":"Bing-Jing Li, Chih-Hsiang Chang, Y. Su, K. Gan, Jianghui Hong","doi":"10.1109/ISNE.2010.5669200","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669200","url":null,"abstract":"A novel CNT/SiC/epoxy composite was proposed and demonstrated as adhesive joining element and heat dissipation media for HB-LEDs. Junction temperature, luminous intensity and forward voltage were measured for varied combinations in the composites. The experimental results showed that the epoxy with 30 wt% of SiC and 5 wt% of MWCNTs had the best thermal properties. Comparing to commercial epoxy, the CNT/SiC/ epoxy could decrease junction temperature from 123 °C to 93°C and thermal resistance from 81 °C /W to 65 °C/W.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127326811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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