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2010 International Symposium on Next Generation Electronics最新文献

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A new type of CMOS inverter with Lubistor load and NMOS driver 采用Lubistor负载和NMOS驱动的新型CMOS逆变器
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669181
Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Cheng-Hsin Chen
{"title":"A new type of CMOS inverter with Lubistor load and NMOS driver","authors":"Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Cheng-Hsin Chen","doi":"10.1109/ISNE.2010.5669181","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669181","url":null,"abstract":"This paper presents a non-conventional CMOS device, which is composed of an nMOSFET and a tunneling field effect transistor (TFET) for driver and load. Based on the measurement data of TFET device published, we have for the first time drawn the Q line of the new designed CMOS compared with the conventional CMOS to verify its feasibility. The static power consumption of it can be optimized and reduced to 4.6E–8 A, and all of the logic operations are correct and have enough swing for manipulating its following operation. Due to its unique structure and the output node being shared by the load and the driver, the integration density of it can be reduced dramatically. The area benefit thus more than 58.5% has been achieved compared with the conventional CMOS layout. In addition, the delay time is improved more than 63%.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129793221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Conditional capacitor averaging technique to reduce nonlinearity induced by capacitor mismatch in 2.5-bit/stage pipelined ADCs 基于条件电容平均技术的2.5位/级流水线adc中由电容失配引起的非线性
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669178
Tz-Jing Shau, Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang
{"title":"Conditional capacitor averaging technique to reduce nonlinearity induced by capacitor mismatch in 2.5-bit/stage pipelined ADCs","authors":"Tz-Jing Shau, Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang","doi":"10.1109/ISNE.2010.5669178","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669178","url":null,"abstract":"This paper presents a conditional capacitor averaging technique to enhance the linearity of 2.5-bit/stage high-resolution pipelined ADCs with capacitor mismatch. Design concepts of capacitor averaging and sorting techniques are employed to mitigate the error effect of capacitor mismatch. Moreover, the sorted capacitors and digital-to-digital converter (DAC) voltages in a 2.5-bit multiplying analog-to-digital converter (MDAC) are well configured to further enhance the linearity of the pipelined ADC. Only slight circuit modification of an MDAC and minor additional digital circuits are required for a pipelined ADC with the proposed technique. Simulation results demonstrate that dynamic and static performances of a 14-bit 2.5-bit/stage pipelined ADCs are improved significantly compared with previous techniques.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126280670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improvement of stop-band attenuation for the Sallen-Key low-pass filter 萨伦键低通滤波器阻带衰减的改进
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669175
Hsin-Wen Ting, Hung-Yu Wang
{"title":"Improvement of stop-band attenuation for the Sallen-Key low-pass filter","authors":"Hsin-Wen Ting, Hung-Yu Wang","doi":"10.1109/ISNE.2010.5669175","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669175","url":null,"abstract":"A Sallen-Key low-pass filter configuration with improved stop-band attenuation is presented. The proposed configuration simply connects an additional capacitor which is in parallel to the filter's output to effectively reduce the high-frequency impedance and consequently the undesired high-frequency feedthrough. The relationship between the additional capacitor and high-frequency feedthrough is also investigated to verify its feasibility. The proposed Sallen-Key low-pass filter configuration combines the advantages of simplicity and improved stop-band attenuation which make it attractive for practical application. The simulation and measurement results also confirm the theoretical prediction.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124480140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 100Ms/s 12-bit 1.8V low power switched capacitor class A/B sample-and-hold amplifier 100Ms/s 12位1.8V低功率开关电容A/B类采样保持放大器
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669172
Ko-Chi Kuo, Bo Chen
{"title":"A 100Ms/s 12-bit 1.8V low power switched capacitor class A/B sample-and-hold amplifier","authors":"Ko-Chi Kuo, Bo Chen","doi":"10.1109/ISNE.2010.5669172","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669172","url":null,"abstract":"The sample and hold amplifier plays an important role in the front end of an analog to digital converter. In this work, a low power, high resolution, and high speed sample and hold amplifier is presented. The architecture of the proposed mainly adapts the class A/B folded cascode amplifier with a gain boosting technique and a switch capacitor common mode feedback scheme. The performance comparisons among different designs show that the proposed work achieves the lowest power consumption. The operation speed of the proposed design is 100Ms/s for a 12-bit resolution ADC by using the TSMC 0.18-µm CMOS technology process and 1.8V power supply.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125302228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the interface between QEMU and SystemC for hardware modeling QEMU与SystemC之间的接口，实现硬件建模
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669197
Tse-Chen Yeh, Ming-Chao Chiang
{"title":"On the interface between QEMU and SystemC for hardware modeling","authors":"Tse-Chen Yeh, Ming-Chao Chiang","doi":"10.1109/ISNE.2010.5669197","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669197","url":null,"abstract":"In this paper, we present an interface for connecting the master/slave ports of hardware modeled in SystemC to a QEMU and SystemC based virtual platform. The virtual platform uses QEMU as the instruction-accurate instruction set simulator (IA-ISS) and is capable of running a full-fledged operating system such as Linux. The proposed interface enables the hardware modeled in SystemC to access hardware modeled in QEMU; thus, it can be used to facilitate the co-design of diverse hardware models and device drivers at the early stage of Electronic System Level (ESL) design flow. Our experimental results—of using Direct Memory Access Controller (DMAC) with two master ports and one slave port as an example—show that the proposed interface makes it possible for migrating hardware models from QEMU to SystemC and for cross verifying the hardware models and device drivers. Moreover, the virtual platform is capable of providing instruction-accurate statistics, thus making it easy for evaluating the performance of the hardware models and for design space exploration.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121880128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications 用于射频/模拟应用的无结伪三栅极垂直mosfet的研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669190
Yu-Che Chang, Jyi-Tsong Lin, Y. Eng, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai, Yi-Hsuan Fan
{"title":"Study of junctionless pseudo tri-gate vertical MOSFETs for RF/analog applications","authors":"Yu-Che Chang, Jyi-Tsong Lin, Y. Eng, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai, Yi-Hsuan Fan","doi":"10.1109/ISNE.2010.5669190","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669190","url":null,"abstract":"In this study, junctionless technology employed for fabricating pseudo tri-gate vertical (PTGV) MOSFETs is proposed and the RF/analog performance is also investigated and demonstrated. According to simulation results, the excellent performances such as high transconductance (gm), high cut-off frequency (ƒT), and high transconductance generation factor (gm/Id) are achieved. The numerical results also provide a prediction of an 8nm gate length PTGV and JPTGV for RF applications.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterisation of new vertical MOSFETs with recessed gate 新型嵌入式栅极垂直mosfet的特性研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669193
C. Kuo, Jyi-Tsong Lin, Y. Eng, Yi-Hsuan Fan
{"title":"Characterisation of new vertical MOSFETs with recessed gate","authors":"C. Kuo, Jyi-Tsong Lin, Y. Eng, Yi-Hsuan Fan","doi":"10.1109/ISNE.2010.5669193","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669193","url":null,"abstract":"This study presents a new vertical MOSFET with recessed gate (RG). Based on the TCAD simulation results, our proposed VMOS structure can gain reduced parasitic capacitance (compared to the conventional VMOS, both Cgd and Cgs can be reduced about 12% and 38.78%, respectively at VDs =1.0 V), improved drain saturation current, and free kink characteristics, in comparison to a conventional VMOS structure. Moreover, the short-channel characteristics of RGVMOS which is modified from the EGVMOS are still acceptable. Most importantly, the manipulation of fabricating this newly proposed structure is enhanced mainly owing to the semicircle gate scheme.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132485178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-cost design of reciprocal function units using shared multipliers and adders for polynomial approximation and Newton Raphson interpolation 使用共享乘法器和加法器进行多项式近似和牛顿·拉夫森插值的互反函数单元的低成本设计
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669204
Shen-Fu Hsiao, Chia-Sheng Wen, Ming-Yu Tsai
{"title":"Low-cost design of reciprocal function units using shared multipliers and adders for polynomial approximation and Newton Raphson interpolation","authors":"Shen-Fu Hsiao, Chia-Sheng Wen, Ming-Yu Tsai","doi":"10.1109/ISNE.2010.5669204","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669204","url":null,"abstract":"A hybrid method of computing reciprocal is presented by combining the degree-two piecewise polynomial interpolation method and a Newton-Raphson iteration. The degree-two piecewise method is used to obtain an initial approximation for the subsequent Newton-Raphson operations. Architecture for the proposed hybrid method is designed considering the hardware sharing of the composing multipliers in the sub-word level, leading to significant improvement in area cost compared to conventional table-based designs and other hybrid approaches.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129529294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Suppression of random-dopant-induced characteristic fluctuation in 16 nm MOSFET devices using dual-material gate 双材料栅极抑制随机掺杂诱导的16nm MOSFET器件特性波动
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669139
C. Yiu, Yong-Yue Ciou, R. Chang, Kuo-Fu Lee, Hui-Wen Cheng, Yiming Li
{"title":"Suppression of random-dopant-induced characteristic fluctuation in 16 nm MOSFET devices using dual-material gate","authors":"C. Yiu, Yong-Yue Ciou, R. Chang, Kuo-Fu Lee, Hui-Wen Cheng, Yiming Li","doi":"10.1109/ISNE.2010.5669139","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669139","url":null,"abstract":"In this work, we for the first time explore the dual material gate (DMG) and inverse DMG devices for suppressing random dopant fluctuation (RDF)-induced characteristics fluctuation in 16-nm MOSFET devices. The physical mechanism of DMG devices to suppress RDF are investigated and discussed. The improvement of DMG for suppressing the RDF-induced Vth, Ion, and Ioff fluctuation are 28%, 12.3%, and 59%, respectively.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131431938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length 不同埋置氧化物和栅长非经典单极CMOS的数值研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669137
Chih-Hung Sun, Jyi-Tsong Lin, Hsuan-Hsu Chen, Y. Eng, C. Kuo, Tze-Feng Chang, Chun-Yu Chen, Po-Hsieh Lin, Hsien-Nan Chiu
{"title":"Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length","authors":"Chih-Hung Sun, Jyi-Tsong Lin, Hsuan-Hsu Chen, Y. Eng, C. Kuo, Tze-Feng Chang, Chun-Yu Chen, Po-Hsieh Lin, Hsien-Nan Chiu","doi":"10.1109/ISNE.2010.5669137","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669137","url":null,"abstract":"In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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