Chih-Hung Sun, Jyi-Tsong Lin, Hsuan-Hsu Chen, Y. Eng, C. Kuo, Tze-Feng Chang, Chun-Yu Chen, Po-Hsieh Lin, Hsien-Nan Chiu
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Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length
In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the common electrodes areas are shared, the layout area can be reduced more than 71%, which leads to significantly increase on the packaging density of CMOS circuits.
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