Implementation of floating-point CORDIC rotation and vectoring based on look up tables and multipliers

Abstract

A unified design is presented that can execute floating-point CORDIC operations in both rotation and vectoring modes with significantly reduced computation latency. Unlike previous pipelined CORDIC implementations usually requiring a sequence of micro-rotation stages proportional to bit accuracy, the proposed design consists of only two stages, coarse and fine stages, with each stage realized using ROM, adders, and multipliers. The bit-widths of the composing hardware components are also optimized to minimize the cost while maintaining the computation accuracy. The proposed design can be applied to applications that require high-precision arithmetic operations with large data representation ranges, such as 3D graphics acceleration.