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The 17th Annual SEMI/IEEE ASMC 2006 Conference最新文献

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Incorporating SIMS Structures in Product Wafers in Order to Perform SIMS and other Material Analysis and Achieve Wafer Level Information about the Front-End Processing 将SIMS结构整合到产品晶圆中，以执行SIMS和其他材料分析，并获得有关前端加工的晶圆级信息
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638717
T. Budri, L. Krott, N. Patel, A. Smith, B. Gurcan, K. Crocker, R. Supczak, C. Printy
{"title":"Incorporating SIMS Structures in Product Wafers in Order to Perform SIMS and other Material Analysis and Achieve Wafer Level Information about the Front-End Processing","authors":"T. Budri, L. Krott, N. Patel, A. Smith, B. Gurcan, K. Crocker, R. Supczak, C. Printy","doi":"10.1109/ASMC.2006.1638717","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638717","url":null,"abstract":"In this paper, we summarize how the introduction of SIMS structures near the global alignment marks of product wafers serve as an additional way to acquire detailed analytical information about front-end processing and can minimize product yield loss without waiting for metal 1 processing when electrical testing (ET) becomes possible","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121694246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Development of the Non-contact Electrical Leakage Property Measurement System for the High-K Dielectric Materials on DRAM Capacitors DRAM电容器高k介电材料非接触漏电性能测量系统的研制
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638715
Yusin Yang, Byung Sug Lee, Misung Lee, C. Jun, Tae Sung Kim
{"title":"The Development of the Non-contact Electrical Leakage Property Measurement System for the High-K Dielectric Materials on DRAM Capacitors","authors":"Yusin Yang, Byung Sug Lee, Misung Lee, C. Jun, Tae Sung Kim","doi":"10.1109/ASMC.2006.1638715","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638715","url":null,"abstract":"We have used the non-contact electrical property measurement system to characterize the electrical leakage property of high-K materials such as Al2O3 and HfO2 on a patterned wafer. The basic technology is to measure the surface voltage with micro Kelvin probe after the corona charge deposition on a measurement area. Because of the charge decay through a dielectric material, voltage-time spectra follow exponential time dependence that is the characteristic of leakage induced charge decay. We have measured the electrical leakage property of the storage capacitors on the direct cell area of DRAM device. The measured electrical leakage property can be classified according to the thickness of Al2O3 and HfO2. Since the electrical leakage property depends on a thickness of a dielectric material, voltage-time spectra show different shapes according to the HfO2 thickness. Using the technology, we can monitor the electrical leakage property of the storage capacitors of high-K materials on the direct cell area","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114416321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
First Look at Across-chip Performance Variation Using Non-Contact, Performance-Based Metrology 首先看看使用非接触式、基于性能的计量的跨芯片性能变化
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638768
M. Babazadeh, J. Estabil, B. Borot, G. Johnson, N. Pakdaman, W. Doedel, J. Vickers, G. Steinbrueck, J. Galvier
{"title":"First Look at Across-chip Performance Variation Using Non-Contact, Performance-Based Metrology","authors":"M. Babazadeh, J. Estabil, B. Borot, G. Johnson, N. Pakdaman, W. Doedel, J. Vickers, G. Steinbrueck, J. Galvier","doi":"10.1109/ASMC.2006.1638768","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638768","url":null,"abstract":"We report on the first non-contact, non-destructive performance measurements of embedded ring oscillators. Measurements are made on inside the die active area as early as metal 1. A 90nm logic CMOS technology was used for this work. We have measured residual across-field performance variation separate from and of opposite sense to wafer uniformity. This effect cannot be extrapolated from scribe measurements","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117246344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in a Technology for Volume Semiconductor Manufacturing 大帕累托:在量产半导体制造技术中识别和量化产量诋毁者的方法
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638792
Z. Berndlmaier, J. Winslow, R. Desineni, A. Blauberg, B. Chu
{"title":"The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in a Technology for Volume Semiconductor Manufacturing","authors":"Z. Berndlmaier, J. Winslow, R. Desineni, A. Blauberg, B. Chu","doi":"10.1109/ASMC.2006.1638792","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638792","url":null,"abstract":"A method of communicating a unified pareto, we call \"Grand Pareto\", for technology-wide defects that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting in identifying key yield detractors for several high-end microprocessors in volume production","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114494116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Cycle Time Approximations for the G/G/m Queue Subject to Server Failures and Cycle Time Offsets with Applications 受服务器故障影响的G/G/m队列的周期时间近似和应用程序的周期时间偏移
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638777
J. R. Morrison, D.P. Martin
{"title":"Cycle Time Approximations for the G/G/m Queue Subject to Server Failures and Cycle Time Offsets with Applications","authors":"J. R. Morrison, D.P. Martin","doi":"10.1109/ASMC.2006.1638777","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638777","url":null,"abstract":"Approximate queueing formulae are often employed for the practical evaluation of manufacturing system performance. Common approximations do not fully address practical issues such as idle tools with work in queue, travel time between stages of production, removal of lots from queue pending process issue resolution and the tendency of lots to defect from a failed server in favor of an equivalent available server. In this paper, approximate queueing formulae are proposed which extend popular existing formulae. To test the quality of the proposed approximations, data from production toolsets in IBM's 200mm semiconductor manufacturing fabricator is considered. It is demonstrated that the approximations perform well on the toolsets studied","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":" 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133420846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Achieving Reduced Production Cycle Times Via Effective Control of Key Factors of the P-K Equation 通过对P-K方程关键因素的有效控制，实现缩短生产周期
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638738
A. Kalir, S. Bouhnik
{"title":"Achieving Reduced Production Cycle Times Via Effective Control of Key Factors of the P-K Equation","authors":"A. Kalir, S. Bouhnik","doi":"10.1109/ASMC.2006.1638738","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638738","url":null,"abstract":"In the current environment of flash semiconductor market, competitive cycle times are the key to success. Cycle time (CT) reduction can be achieved by process time elimination and equipment performance improvement, but also by optimized WIP management policy. In this paper, we discuss how significant CT reductions are attained via the effective change of parameter values of the governing WIP management policy of a semiconductor factory. A full factorial design of experiments (DOE) was performed, and several parameters were examined. The impact on the coefficient of variability of departure rate (CDR) and CT was evaluated. Results have clearly shown that by changing the values of these parameters, significant cycle time reductions of up to 13% can be achieved","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133433392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Metrology Delay Time Reduction in Lithography with an Enhanced AMHS using Local FOUP Buffering 使用局部FOUP缓冲的增强AMHS光刻测量延迟时间减少
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638735
V. Shah, E. Englhardt, S. Koshti, H. Armer
{"title":"Metrology Delay Time Reduction in Lithography with an Enhanced AMHS using Local FOUP Buffering","authors":"V. Shah, E. Englhardt, S. Koshti, H. Armer","doi":"10.1109/ASMC.2006.1638735","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638735","url":null,"abstract":"An enhanced automated material handling system (AMHS) that uses a local FOUP buffer at each tool is presented as a method of enabling lot size reduction and parallel metrology sampling in the photolithography (litho) bay. The local FOUP buffers can be integrated with current OHT AMHS systems in existing fabs with little or no change to the AMHS or process equipment. The local buffers enhance the effectiveness of the OHT by eliminating intermediate moves to stockers, increasing the move rate capacity by 15-20%, and decreasing the loadport exchange time to 30 seconds. These enhancements can enable the AMHS to achieve the high move rates compatible with lot size reduction down to 12-15 wafers per FOUP. The implementation of such a system in a photolithography bay could result in a 60-74% reduction in metrology delay time, which is the time between wafer exposure at a litho tool and collection of metrology and inspection data.","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130442297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Evaluating deep trench profile by Fourier Transform Infrared spectroscopy 用傅里叶变换红外光谱评价深沟剖面
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638741
M. Wang, T. Cheng, Chung-I Chang, Tings Wang
{"title":"Evaluating deep trench profile by Fourier Transform Infrared spectroscopy","authors":"M. Wang, T. Cheng, Chung-I Chang, Tings Wang","doi":"10.1109/ASMC.2006.1638741","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638741","url":null,"abstract":"As design rule shrinking, it's more challenged to keep the enough capacitance for DRAM device requirement. For deep trench DRAM, one of methods supplied enough capacitance of providing deeper trench. Currently, the trench depth is over 6 mum for the 512M DRAM. In order to meet this stringent requirement, we need to care about not only the profile of deep trench (DT) but also the enough depth. Due to this high aspect ratio process is roughly over 60, it is very difficult for current inline defect monitor's method to check the abnormal trench profile. Traditional methods for verifying DT profile must destroy the wafer by the physical failure analysis. The wafer is analyzed by SEM (scanning electron microscope) to check DT cross-section or FIB (focus ion beam) to inspect slice view image. These methods provide difficultly the whole wafer map message for DT profile, offering merely random-cross-section inspection. Now we provide an inline-fast-effective method by the IR spectrum's analysis that can give the available message to monitor the DT profile","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131016867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Infusion processing for advanced transistor manufacturing 用于先进晶体管制造的灌注加工
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638746
W. Skinner, M. Gwinn, J. Hautala, T. Kuroi
{"title":"Infusion processing for advanced transistor manufacturing","authors":"W. Skinner, M. Gwinn, J. Hautala, T. Kuroi","doi":"10.1109/ASMC.2006.1638746","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638746","url":null,"abstract":"Production capable infusion processing equipment for ultra shallow doping and surface engineering is now available. Shrinking device dimensions require extremely shallow doping for many applications. New techniques are necessary in order to manufacture source drain extensions (SDE) and for DRAM poly doping. Channel engineering is required for advanced gates. High throughput, tight process control and low contamination are required from the process equipment. Epion Corporation has developed the nFusiontrade 300mm doping system that offers solutions for these applications. The production worthiness is characterized with high doping rates, long term repeatability, depth control and low contamination","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122412796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Empirical Study of Photomask Manufacturing Productivity 光掩膜生产效率的实证研究
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638798
C. N. Berglund, C. Weber, C. Castilla
{"title":"An Empirical Study of Photomask Manufacturing Productivity","authors":"C. N. Berglund, C. Weber, C. Castilla","doi":"10.1109/ASMC.2006.1638798","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638798","url":null,"abstract":"A survey-based, empirical study of photomask manufacturing productivity has led to a few significant conclusions. Firstly, the wide variation in the productivity indicators from company to company suggests that all participants may have significant cost-reduction opportunities within their operations. Secondly, high downtime of pattern generation tools is limiting productivity. Thirdly, producing smaller feature sizes is correlated to an investment in engineering and experimentation capacity. It could not be confirmed that photomask manufacturers are successfully taking advantage of economies of scale","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126760185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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