Incorporating SIMS Structures in Product Wafers in Order to Perform SIMS and other Material Analysis and Achieve Wafer Level Information about the Front-End Processing

Abstract

In this paper, we summarize how the introduction of SIMS structures near the global alignment marks of product wafers serve as an additional way to acquire detailed analytical information about front-end processing and can minimize product yield loss without waiting for metal 1 processing when electrical testing (ET) becomes possible