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A New Category of Particles at 65nm Technology and Below 65纳米及以下技术的新一类粒子
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638787
D. Rathei, A. Neuber
{"title":"A New Category of Particles at 65nm Technology and Below","authors":"D. Rathei, A. Neuber","doi":"10.1109/ASMC.2006.1638787","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638787","url":null,"abstract":"We aligned experience from yield analysis with knowledge from aerosol physics and found strong evidence that semiconductor manufacturers have face a new category of particles in the next technology nodes at and below 65nm","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126187794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
AMHS Software Solutions to Increase Manufacturing System Performance 提高制造系统性能的AMHS软件解决方案
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638774
T. Wiethoff, C. Swearingen
{"title":"AMHS Software Solutions to Increase Manufacturing System Performance","authors":"T. Wiethoff, C. Swearingen","doi":"10.1109/ASMC.2006.1638774","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638774","url":null,"abstract":"In this work, AMHS performance challenges in a ramping 300mm wafer fabrication facilities are identified. Software solutions are described as viable, low cost, minimal fab disruption alternatives to both new and long standing AMHS challenges. Technical design and realized cost, performance, and utilization gains will be shared for various successful software enhancements to the existing fabrication facility's automation software. The conclusion will outline at a high level some future opportunities in this space and challenges for managing these complex software systems","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125412704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Robust Real-Time Thin Film Thickness Estimation 鲁棒实时薄膜厚度估计
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638724
C. Kiew, A. Tay, W.K. Ho, K. W. Lim, J.H. Lee
{"title":"Robust Real-Time Thin Film Thickness Estimation","authors":"C. Kiew, A. Tay, W.K. Ho, K. W. Lim, J.H. Lee","doi":"10.1109/ASMC.2006.1638724","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638724","url":null,"abstract":"The dissolution of photoresist in developer solution often leads to changes in the chemical composite of the solution which hinder film thickness estimation. This paper addresses this issue by proposing a modified fringe order computation (MFOC) method which analyses reflected light intensity data acquired using commercially available optical spectrometry system. MFOC uses simple arithmetic operations and is capable of computing film thickness at real-time. It is more reliable as compared to other methods during develop step in microlithography process","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116220617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimization of Ultrasonic Cleaning for Erosion-Sensitive Microelectronic Components 微电子腐蚀敏感元件的超声波清洗优化
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638750
R. Nagarajan, M. Diwan, P. Awasthi, A. Shukla, P. Sharma, M. Goodson, S. Awad
{"title":"Optimization of Ultrasonic Cleaning for Erosion-Sensitive Microelectronic Components","authors":"R. Nagarajan, M. Diwan, P. Awasthi, A. Shukla, P. Sharma, M. Goodson, S. Awad","doi":"10.1109/ASMC.2006.1638750","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638750","url":null,"abstract":"In this paper, we describe an experimental study undertaken to investigate ultrasonic fields in the frequency range 58-192 kHz with respect to their surface cleaning and erosion potential. Measurements are performed using three different methods - gravimetric weight-loss, surface profilometry, and precision turbidimetry - to assess these mechanisms for a variety of materials, including semiconductors. Conclusions are drawn regarding the nature of interaction between high-frequency, high-intensity ultrasonic fields and immersed surfaces. Recommendations are provided for optimal settings to maximize surface cleanability and minimize erodibility of sensitive substrates","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Equipment Productivity Enhancement by SMC (Statistical Machine Control) Application on Furnace Area SMC(统计机床控制)在炉区提高设备生产率的应用
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638765
Chun-Yao Wang, B. Huang, Chia-Ming Kuo, A. Ku
{"title":"Equipment Productivity Enhancement by SMC (Statistical Machine Control) Application on Furnace Area","authors":"Chun-Yao Wang, B. Huang, Chia-Ming Kuo, A. Ku","doi":"10.1109/ASMC.2006.1638765","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638765","url":null,"abstract":"In this work, we clearly address the strategies of monitor and via statistic machine control (SMC) on furnace process at ProMOS technology, DRAM manufactory, including low pressure and atmosphere pressure process. Especially for LPCVD nitride deposition process, particle and condense in the piping which was formed by by-product, NH4Cl, is an undesired factor to affect process stability. This work have demonstrated four strategies of statistic machine control (SMC) models, (A)VG2 clog (B) SV clog (C) VV1 clog (D) FCV angle control, to predict the timing and location of by-product clog at LPCVD furnace nitride processes and warm us when the by-produce condense had generated and the clog was accrued. Further more, to predict the schedule to clean the powder by short corrective action. It was found that the counts of leak check fail were obviously getting improvement for different nitride process equipments, the overall improvement of leak check fail average count is 15.8 time/month before May to below 4 time/month. The impacted lots also were reduced 79.3% which equals to 2.6 K wafers move gaining per month. With the reduction of tool down time and maintenance, the productivity can be increased and manpower and cost was saved","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124595378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single Electron Transistor Fabrication using Focused Ion Beam direct write technique 聚焦离子束直写技术制造单电子晶体管
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638756
P. Santosh Kumar Karre, P. Bergstrom, M. Govind, S. Karna
{"title":"Single Electron Transistor Fabrication using Focused Ion Beam direct write technique","authors":"P. Santosh Kumar Karre, P. Bergstrom, M. Govind, S. Karna","doi":"10.1109/ASMC.2006.1638756","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638756","url":null,"abstract":"We report on the fabrication of single electron transistors using focused ion beam (FIB) etching technology. Single electron transistors (SETs) are comprised of small conducting islands called the Coulomb blockade islands and tunnel junctions, allowing quantum mechanical tunneling of electrons onto and off of the islands. The typical random deposition of islands makes it difficult to fabricate SETs with the same parameters, because the position of the island strongly impacts the tunnel capacitance and resistance. We report the use of maskless FIB direct write technology to fabricate SETs, producing quantum islands less than 50nm in diameter. The FIB direct writing technique allows the exact placement of islands at a desired location in order to better control the device parameters. The initial characteristics of the devices, at room temperature, show that the Coulomb oscillations are smeared out, as expected for this condition. The conductance displays an asymptotic behavior, which is attributed to the operation of the SET in the strong tunnel regime and to its operation at room temperature","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124229307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Best Known Method for Forming a Multi-Fab Cost Reduction Infrastructure and Applying Innovative Cost Reduction Techniques in Diffusion. 形成多晶圆厂成本降低基础设施的最佳方法及在扩散中应用创新的成本降低技术。
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638791
H. Hershkovitz, M. Batra
{"title":"A Best Known Method for Forming a Multi-Fab Cost Reduction Infrastructure and Applying Innovative Cost Reduction Techniques in Diffusion.","authors":"H. Hershkovitz, M. Batra","doi":"10.1109/ASMC.2006.1638791","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638791","url":null,"abstract":"In advanced semiconductor manufacturing, capital equipment depreciation drives a significant fixed cost in producing products. In order to remain competitive in the flash memory segment cost reduction aspects need to be in focus and it is imperative to put plans and actions in place in order to reduce the wafer cost in the early stages of the technology development. This paper presents a best known method (BKM) that describes a multi-factory cost infrastructure. The development and implementation of this BKM resulted in cost reduction, and specifically focused on the various cost reduction techniques applied in the diffusion clean room functional area. To date, 22% capital cost reduction has been attained for Intel Corporation in the diffusion area between Q1 '04 to Q2 '05, across the 200 mm network","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130197184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Si Crystallization Monitoring Using EBSD Technique 利用EBSD技术监测硅结晶
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638753
Young-Bin Yoon, J. Lim, C. Jun
{"title":"Si Crystallization Monitoring Using EBSD Technique","authors":"Young-Bin Yoon, J. Lim, C. Jun","doi":"10.1109/ASMC.2006.1638753","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638753","url":null,"abstract":"The stacked structure of a semiconductor device is aggressively tried to solve the limit of device size, which has been reduced by the condensation of device design. To make the stacked device, we should make single crystal Si layer for upper transistors using the crystallization of amorphous Si layer deposited on the thick ILD layer. The fast process feedback is strongly needed to optimize and to check the process. We proposed electron back scattered diffraction (EBSD) method to monitor the Si crystallization process. The crystallization of a-Si film is monitored using the crystalline orientation map, the (001) crystal direction map and area, and the grain size distribution. For the mass production of devices, we are developing an in-fab metrology tool of EBSD","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134040202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
FAROS - Fully Automated Robotic Sorter Cluster Use for Single Wafer Tracking in Semiconductor Manufacturing FAROS -用于半导体制造中单晶圆跟踪的全自动机器人分选机集群
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638742
F. Heinlein, A. Kuehn
{"title":"FAROS - Fully Automated Robotic Sorter Cluster Use for Single Wafer Tracking in Semiconductor Manufacturing","authors":"F. Heinlein, A. Kuehn","doi":"10.1109/ASMC.2006.1638742","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638742","url":null,"abstract":"In this paper, we describe the beneficial combination of a fully automated robotic sorter approach called FAROS and the single wafer tracking concept for Infineon's mid nineties 8\" wafer fab in Dresden, Germany. We describe the system itself, its implementation, and utilization within a single wafer tracking front end manufacturing environment including randomization. A discussion of typical performance indicators for semiconductor production equipment sheds light on the capability and economics of the FAROS system","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134132522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improving Gate Poly CD Bias Control Using Voltage Controller Interface 利用电压控制器接口改进栅极多晶硅偏置控制
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638745
C. Daigle
{"title":"Improving Gate Poly CD Bias Control Using Voltage Controller Interface","authors":"C. Daigle","doi":"10.1109/ASMC.2006.1638745","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638745","url":null,"abstract":"In this paper, an etching tool hardware solution is presented for minimizing poly gate width variation induced by lower RF system equipment changes","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126152266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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