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Low-K and Interconnect Stacks -- a Status Report 低k和互连堆栈—状态报告
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638733
D. James
{"title":"Low-K and Interconnect Stacks -- a Status Report","authors":"D. James","doi":"10.1109/ASMC.2006.1638733","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638733","url":null,"abstract":"One of the interesting aspects of the migration of low-k into state-of-the-art processes is that almost every manufacturer does it differently - as a generality, there seems to be a greater variety in the detail of low-k implementation than there was in the metal-dielectric structures in the \"good old days\" of aluminium metallization. Some manufacturers use a simple two-layer dielectric, dual-damascene matrix in their interconnect stack, and others have complex multilayers with single-damascene metal tracks and vias. Chipworks, as a supplier of competitive intelligence to the semiconductor and electronics industries, monitors the evolution of chip processes as they come into commercial production. Chipworks has obtained parts from leading edge manufacturers, and performed structural analyses to examine the features and manufacturing processes of the devices. The paper discusses how low-k dielectrics have been used by various vendors, and gives a comparison of their different back-end-of-line technologies. The paper will detail the physical structures we have analyzed, and also examine the different approaches to the use of low-k dielectric materials","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130548735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
MES Validation using FAB-wide Equipment Simulation 使用fab范围内的设备模拟进行MES验证
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638776
Khiam Wei Ow, Aik Giap Koh, H. K. Khoo, Chih Chuan Shih
{"title":"MES Validation using FAB-wide Equipment Simulation","authors":"Khiam Wei Ow, Aik Giap Koh, H. K. Khoo, Chih Chuan Shih","doi":"10.1109/ASMC.2006.1638776","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638776","url":null,"abstract":"Introducing significant changes (or even a new system) to production systems (i.e. manufacturing execution system) on a production floor has always been a challenge. A key issue is the need to conduct high confidence testing validating the correctness and performance of the new system. Currently, production requirements (i.e. lack of equipment time) usually limit the quantity and quality of the tests we can conduct. We have devised an approach to provide a highly realistic testing environment by simulating FAB wide equipments interacting with the MES system via the equipment integration (EI) components just as it would in actual production. This way, we are able to validate the target production system with high confidence without the need of actual equipment time","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126862017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Choosing Optimal Control Structure for Run-to-Run Control - A Thin Film Example 运行到运行控制的最优控制结构选择——以薄膜为例
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638767
N. S. Patel, R. Rajagopal
{"title":"Choosing Optimal Control Structure for Run-to-Run Control - A Thin Film Example","authors":"N. S. Patel, R. Rajagopal","doi":"10.1109/ASMC.2006.1638767","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638767","url":null,"abstract":"This paper presents a case study for determining the optimal structure of the run-to-run control algorithm for thin film processes. Specifically, the expected process disturbance characteristics are used to determine the nature of the control strategy. Two examples of thin film processes are considered $(i) one involving a simple one-step deposition, and (ii) the other involving two deposition steps, with feedback only possible at the end of both the steps. This paper shows that a unified control structure is capable of handling multiple process types, which traditionally have used different controllers (in terms of their structure), especially in the presence of process shifts and drifts. Furthermore, the paper will also touch upon how the choice of the controller structure depends on the number of context dependent free parameters in the model","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124861119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Smaller is Better? Maximization of Good Chips per Wafer by Co-Optimization of Yield and Chip Area 越小越好?通过共同优化良率和芯片面积来最大化每片晶圆的优质芯片
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638786
H. Melzner
{"title":"Smaller is Better? Maximization of Good Chips per Wafer by Co-Optimization of Yield and Chip Area","authors":"H. Melzner","doi":"10.1109/ASMC.2006.1638786","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638786","url":null,"abstract":"The two factors defining number of good chips that can be picked from a wafer are yield and number of chips per wafer. Number of chips is primarily defined by chip area -together with details such as die aspect ratio, kerf width, edge exclusion, and die placement. While yields play the major role once a chip design is finished, in the design phase chip area can still be influenced. It is frequently thought that \"smaller is better\", i.e. a given functionality should be realized on a minimum silicon area. This is certainly true if there are no strong relationships between area and yield. In some cases, however, there are such strong relationships - a good example is redundancy configuration for memory chips or embedded memories. Powerful redundancy typically requires more area, but can boost yield on the other hand. Analog circuits may be more robust and have higher yield if devices are designed larger. Even in logic chips, DfM measures such as via duplication may sometimes increase chip area. In all these cases, an optimum of yield gain versus area growth has to be found. In this paper, we review and discuss some relationships between yield and area and present methods for optimization of good chips per wafer","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Full Field, ArF Immersion Projection Tool 全领域，ArF沉浸投影工具
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638725
S. Owa, K. Shiraishi, S. Nagaoka, T. Fujiwara, Y. Ishii
{"title":"Full Field, ArF Immersion Projection Tool","authors":"S. Owa, K. Shiraishi, S. Nagaoka, T. Fujiwara, Y. Ishii","doi":"10.1109/ASMC.2006.1638725","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638725","url":null,"abstract":"Immersion lithography is rapidly approaching the manufacturing phase. A production-quality exposure tool system with NA = 1.07 (Nikon NSR-S609B) was constructed to target the start of immersion lithography for IC manufacturing in 2006. Its projection optics has very small wave-front aberration and lowest local flare levels. The overlay issue has been analyzed, and its cause was found to be evaporation cooling. With the tandem stage and local fill nozzle implemented in the S609B, we have successfully avoided the evaporation cooling so that the good wet-to-dry mix-and-match overlay data have been obtained. The major part of immersion specific defects is caused by dried water-droplets, i.e. water-marks. The local fill nozzle has eliminated this defectivity by avoiding airflow in the nozzle. In the future, water immersion with NA = 1.30 optics will be used for half-pitch 45 nm manufacturing","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125274411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Can You Reduce the Amount of CDs Measured, While Retaining the Required Sensitivity of Statistical Process Control (SPC)? 在保持统计过程控制(SPC)所需灵敏度的同时，能否减少cd的测量量?
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638769
A. Eidelman, J. Asscher
{"title":"Can You Reduce the Amount of CDs Measured, While Retaining the Required Sensitivity of Statistical Process Control (SPC)?","authors":"A. Eidelman, J. Asscher","doi":"10.1109/ASMC.2006.1638769","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638769","url":null,"abstract":"In this paper, we describe a method of determining the amount of sampling needed for effective process control of photolithographic critical dimensions (CDs) using an advanced statistical approach. This method can also be used for other processes (thin films, CMP, diffusion, ETCH) where SPC is applied","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122449679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Deep Trench Top Collar Oxide Etching for DRAM Manufacturing DRAM制造的深沟顶领氧化物蚀刻技术
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638761
Guowen Zheng, G. Skinner
{"title":"Deep Trench Top Collar Oxide Etching for DRAM Manufacturing","authors":"Guowen Zheng, G. Skinner","doi":"10.1109/ASMC.2006.1638761","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638761","url":null,"abstract":"In the fabrication of deep trenches (DT) used as the storage capacitors in DRAMs, precise formation of the lateral oxide isolation inside the trench $the \"collar\" - is one of the key process modules. The collar formation involves DT top oxide etching following furnace oxide growth. Careful optimization of the most critical oxide etch step is necessary. In this paper, the etch process parameters impacting the net collar oxide removal rate are discussed, followed by etch chamber conditioning optimization. Etch process endpoint challenges and solutions are also investigated","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"14 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122585463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fluctuation Smoothing Production Control at IBM's 200mm Wafer Fabricator: Extensions, Application and the Multi-Flow Production Index (MFPx) IBM 200mm晶圆制造商的波动平滑生产控制:扩展、应用和多流生产指数(MFPx)
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638737
J. R. Morrison, E. Dews, J. LaFreniere
{"title":"Fluctuation Smoothing Production Control at IBM's 200mm Wafer Fabricator: Extensions, Application and the Multi-Flow Production Index (MFPx)","authors":"J. R. Morrison, E. Dews, J. LaFreniere","doi":"10.1109/ASMC.2006.1638737","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638737","url":null,"abstract":"To increase the flexibility of existing production control algorithms and reduce the variation and mean of fabricator cycle times, a fluctuation smoothing for the variation of cycle time (FSVCT) policy was implemented at IBM's 200mm semiconductor wafer fabrication facility. Extensions allowing for products with different cycle times and enabling the change of cycle time targets during production were developed. The policy was named the multi-flow production index (MFPx), reflective of its capabilities. Increased production agility and a controlled variation of cycle time resulted from the implementation","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132593531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Development of a Shock & Vibration Spec for 300mm Wafer AMHS Handling 300mm晶圆AMHS处理冲击与振动规范的开发
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638762
J. Steele, T. Biswas
{"title":"Development of a Shock & Vibration Spec for 300mm Wafer AMHS Handling","authors":"J. Steele, T. Biswas","doi":"10.1109/ASMC.2006.1638762","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638762","url":null,"abstract":"In this work, a technique is presented for establishing and verifying safe vibration and shock limits for preventing cross-slotting of 300mm wafers in FOUPs during AMHS handling. This technique includes establishing the safe limits using a shaker table, calibrating these limits for a particular portable accelerometer, and then using this portable accelerometer to check an AMHS for compliance to these limits","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132799934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Single-Wafer vs. Batch Wet Surface Preparation in BEOL: a Comparison of Polymer Cleans using Inorganic Chemicals in Flash Memory Production BEOL中的单晶片与批量湿表面制备:在闪存生产中使用无机化学品清洗聚合物的比较
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638771
T. Couteau, G. Dawson, J. Halladay, L. Archer
{"title":"Single-Wafer vs. Batch Wet Surface Preparation in BEOL: a Comparison of Polymer Cleans using Inorganic Chemicals in Flash Memory Production","authors":"T. Couteau, G. Dawson, J. Halladay, L. Archer","doi":"10.1109/ASMC.2006.1638771","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638771","url":null,"abstract":"In this paper a specific case study comparing a batch and a single-wafer process using inorganic chemicals to remove post-etch residue (polymer) on flash device wafers is presented. The adoption of polymer cleans using dilute sulfuric-peroxide-HF (DSP+) mixture on a single-wafer SEZ spin processor was reported earlier and has resulted in a significant cost reduction and marked yield improvement at Spansion Fab 25. Initially, the process was introduced for all metal layers and contact layers 2 through 6. Contact 1, however, was performed on a spray batch tool using a sulfuric-per oxide mixture (SPM) followed by an ammonium-peroxide mixture (APM). As part of their continued desire to use single-wafer tools and to diminish the number and quantity of chemicals used in the fab, the effectiveness of the DSP + process on contact 1 was investigated. The results of this investigation are presented here. Detailed wafer metrology and electrical characterization and yield data are discussed","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134211573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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