Low-K and Interconnect Stacks -- a Status Report

Abstract

One of the interesting aspects of the migration of low-k into state-of-the-art processes is that almost every manufacturer does it differently - as a generality, there seems to be a greater variety in the detail of low-k implementation than there was in the metal-dielectric structures in the "good old days" of aluminium metallization. Some manufacturers use a simple two-layer dielectric, dual-damascene matrix in their interconnect stack, and others have complex multilayers with single-damascene metal tracks and vias. Chipworks, as a supplier of competitive intelligence to the semiconductor and electronics industries, monitors the evolution of chip processes as they come into commercial production. Chipworks has obtained parts from leading edge manufacturers, and performed structural analyses to examine the features and manufacturing processes of the devices. The paper discusses how low-k dielectrics have been used by various vendors, and gives a comparison of their different back-end-of-line technologies. The paper will detail the physical structures we have analyzed, and also examine the different approaches to the use of low-k dielectric materials