Smaller is Better? Maximization of Good Chips per Wafer by Co-Optimization of Yield and Chip Area

Abstract

The two factors defining number of good chips that can be picked from a wafer are yield and number of chips per wafer. Number of chips is primarily defined by chip area -together with details such as die aspect ratio, kerf width, edge exclusion, and die placement. While yields play the major role once a chip design is finished, in the design phase chip area can still be influenced. It is frequently thought that "smaller is better", i.e. a given functionality should be realized on a minimum silicon area. This is certainly true if there are no strong relationships between area and yield. In some cases, however, there are such strong relationships - a good example is redundancy configuration for memory chips or embedded memories. Powerful redundancy typically requires more area, but can boost yield on the other hand. Analog circuits may be more robust and have higher yield if devices are designed larger. Even in logic chips, DfM measures such as via duplication may sometimes increase chip area. In all these cases, an optimum of yield gain versus area growth has to be found. In this paper, we review and discuss some relationships between yield and area and present methods for optimization of good chips per wafer