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Evaporation vs. Sputtering of metal layers on the Backside of Silicon wafers 硅片背面金属层的蒸发与溅射
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638731
M. Ciacchi, H. Eder, H. Hirscher
{"title":"Evaporation vs. Sputtering of metal layers on the Backside of Silicon wafers","authors":"M. Ciacchi, H. Eder, H. Hirscher","doi":"10.1109/ASMC.2006.1638731","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638731","url":null,"abstract":"We present the results of the differences observed between evaporated and sputtered backside metallization processes on silicon wafers: these two methods of fabricating metal layers and the activation of the backside semiconductor-metal contact follow different physical mechanisms. Differing crystalline structures of the metal layers can be observed and the thermal budget of the overall process of the wafer is affected in different ways. In this paper, we describe these differences, provide a description of the known physical and mechanical mechanisms and propose some models. Additionally, we report a few production issues and experiences","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122540515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Daily Indicator Review Team (DIRT) 每日指标检讨小组(DIRT)
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638743
D. Camacho, D. Newlon, A. Murphy, M. Moran
{"title":"Daily Indicator Review Team (DIRT)","authors":"D. Camacho, D. Newlon, A. Murphy, M. Moran","doi":"10.1109/ASMC.2006.1638743","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638743","url":null,"abstract":"Sort test systems (STS) quality events limit manufacturing output capability. Sort does not possess an automated process control system. The daily indicator review team (DIRT) was created in Q2 '04 to focus on detection, reaction, and reducing STS quality events with the overall goal of improving sort manufacturing efficiency. This forum has evolved from an engineering led team to a manufacturing led team. This abstract presents the operational and tactical model of the DIRT and illustrates the DIRT's role in the identification of chronic technical issues and the continuous output improvements of the sort test systems","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Deep Trench Resistance and leakage Reduction - Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory 深沟槽电阻和减少泄漏- 300mm工厂大批量DRAM制造中的Poly1掺杂工艺优化
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638795
Minsoo Kim, W. Cooper, B. Simonson, D. Ricks, E. McDaniel, R. Miller, R. Chapman, T. Taylor, R. Fuller
{"title":"Deep Trench Resistance and leakage Reduction - Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory","authors":"Minsoo Kim, W. Cooper, B. Simonson, D. Ricks, E. McDaniel, R. Miller, R. Chapman, T. Taylor, R. Fuller","doi":"10.1109/ASMC.2006.1638795","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638795","url":null,"abstract":"In this paper, we describe the influence of arsenic doped poly-silicon on signal margin and node leakage current of 110 nm deep trench DRAM products. Methods on optimizing both physical and electrical qualities of poly-silicon are presented and challenges of quick electrical characterization of the new process for rapid yield learning are discussed. Finally, how these methods can be applied to other poly layers and to the next generation devices are briefly discussed","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121598389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Semantically Enabled Media in Equipment Service Documentation Leads to Lower Cost Operations 设备服务文档中语义支持的媒体可降低操作成本
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638789
C. Keller, D. Peters, E. Gamez
{"title":"Semantically Enabled Media in Equipment Service Documentation Leads to Lower Cost Operations","authors":"C. Keller, D. Peters, E. Gamez","doi":"10.1109/ASMC.2006.1638789","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638789","url":null,"abstract":"This paper intends to show how an electronic system can be developed and implemented in large factory environments to solve critical problems with regard to storing and retrieving a wide variety of information and media. We show that with semantically enabled media presented via an electronic system, the business of maintaining complex machinery in a volume factory environment can become less costly and more efficient. Not by simply providing access to flat documents but by presenting the information or media, utilizing an application, in ways that fit the needs of the reader or user and allows the consumer of this information to become higher performing. This abstract also intends to articulate the importance of having equipment service information in a format that allows for the information to be utilized in innovative and cost effective ways","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125846592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Blended Learning - Neither Shaken nor Stirred 混合式学习——既不摇也不搅
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638783
B. Simington
{"title":"Blended Learning - Neither Shaken nor Stirred","authors":"B. Simington","doi":"10.1109/ASMC.2006.1638783","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638783","url":null,"abstract":"Blended learning (BL) is a logical extension of the continuum that began with the use of a single instructional medium in a curriculum to the use of multiple media and methods of delivery in instructional units. It has enormous potential for improving learning and it brings with it several challenges regarding its appropriate use and its proliferation. The primary factor in the emergence of blended learning has been the proliferation of personal computers and computer workstations in the workplace coupled with the availability of new computer applications that have greatly improved the ability to produce and deliver quality training interventions to a broad audience. The benefits of adopting a BL approach to training are many and obvious but the challenges involved in shifting to BL are also numerous. This paper explores the promise and the costs of adopting a Blended Learning approach for equipment training in the semiconductor manufacturing environment","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132680014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Dynamic Wet-Furnace Dispatching/Scheduling in Wafer Fab 晶圆厂湿炉动态调度/调度
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638739
M. Ham, M. Raiford, F. Dillard, W. Risner, M. Knisely, J. Harrington, T. Murtha, Hyung Tae Park
{"title":"Dynamic Wet-Furnace Dispatching/Scheduling in Wafer Fab","authors":"M. Ham, M. Raiford, F. Dillard, W. Risner, M. Knisely, J. Harrington, T. Murtha, Hyung Tae Park","doi":"10.1109/ASMC.2006.1638739","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638739","url":null,"abstract":"The pre-cleaning equipment (or wet etch) in semiconductor manufacturing can load more than one dozen lots at one time. Because of the large capacity, the wet etch plays a key role in keeping the line balanced. After the wet etch operation, the wafers go mainly to furnaces, and the remaining goes to dry etch, CVD, photo or back to wet etch. If the wet etch produces the wafers in unbalanced fashion, the downstream equipment can be starved for inventory. Furthermore, there are often queue time restrictions between the wet etch and the downstream step and vice versa. This paper shows the success story of developing and implementing the wet etch scheduler which enables us to insure the proper inventory level at downstream steps and meet the queue time restriction at Samsung Austin Semiconductor","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124340755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Yield Improvement Using a Fast Product Wafer Level Monitoring System 利用快速晶圆液位监控系统提高良率
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638794
C. Hess, M. Saadat, Anand Inani, Yun Lin, H. Matsuhashi, M. Squicciarini, R. Lindley, N. Akiya, E. Kaste
{"title":"Yield Improvement Using a Fast Product Wafer Level Monitoring System","authors":"C. Hess, M. Saadat, Anand Inani, Yun Lin, H. Matsuhashi, M. Squicciarini, R. Lindley, N. Akiya, E. Kaste","doi":"10.1109/ASMC.2006.1638794","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638794","url":null,"abstract":"A Scribe Characterization Vehiclereg (CVreg) test chip has been developed to enable a fast turn around mass production yield monitoring system. The test chip design is being placed within the scribe lines of product chip reticles, efficiently utilizing three-dimensional stacking of test structures. During manufacturing, wafer level testing will be executed using pdFasTestreg to ensure test times below 10 minutes per 300 mm wafer. The measurement data will then be analyzed using pdCVtrade to determine yield predictive data like fail rates and defect densities. Also variability data of layer specific parameters like sheet resistance and contact/via resistance will be extracted. Finally, extensive statistical analysis will be run using dataPOWERtrade to derive correlation to product yield as well as lot equipment history","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129360429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Post Implant Strip Optimization for 90nm and Beyond Technologies 90纳米及以上技术的植入后条带优化
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638770
N. Fuller, A. Santiago, K. Mello, Chienfan Yu, S. Molis
{"title":"Post Implant Strip Optimization for 90nm and Beyond Technologies","authors":"N. Fuller, A. Santiago, K. Mello, Chienfan Yu, S. Molis","doi":"10.1109/ASMC.2006.1638770","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638770","url":null,"abstract":"Optical emission spectroscopy, SEM, and SIMS were used to analyze the modified layer formed during exposure of resist materials to ion implant conditions and to characterize the removal rate of this modified layer upon exposure to various plasma strip chemistries on commercial strip tools. This methodology was used to evaluate candidate strip chemistries for reducing post implant strip defectivity and increasing device functional yield","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127279267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Effect of Wafer Substrate Resistance on Inter Poly Oxide Thickness Variation 晶圆衬底电阻对聚氧化物厚度变化的影响
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638790
J. Towner, J. Naughton
{"title":"The Effect of Wafer Substrate Resistance on Inter Poly Oxide Thickness Variation","authors":"J. Towner, J. Naughton","doi":"10.1109/ASMC.2006.1638790","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638790","url":null,"abstract":"In our mixed signal devices, deposited oxides are used in structures such as poly-poly capacitors. Wafers using highly doped substrates showed good thickness uniformity but uniformity deteriorated as the resistance of the substrate increased. Other factors that increased substrate resistance also increased nonuniformity. Thickness variation was correlated to electrostatic charge imparted to the wafer from poorly grounded wafer handling robotics. This charging likely caused plasma instabilities that promoted the absorption and reaction of the TEOS intermediates","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121714606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Short-Interval Detailed Production Scheduling in 300mm Semiconductor Manufacturing using Mixed Integer and Constraint Programming 基于混合整数和约束规划的300mm半导体制造短间隔详细生产调度
The 17th Annual SEMI/IEEE ASMC 2006 Conference Pub Date : 2006-05-22 DOI: 10.1109/ASMC.2006.1638740
R. Bixby, R. Burda, D. Miller
{"title":"Short-Interval Detailed Production Scheduling in 300mm Semiconductor Manufacturing using Mixed Integer and Constraint Programming","authors":"R. Bixby, R. Burda, D. Miller","doi":"10.1109/ASMC.2006.1638740","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638740","url":null,"abstract":"Fully automated 300mm manufacturing requires the adoption of a real-time lot dispatching paradigm. Automated dispatching has provided significant improvements over manual dispatching by removing variability from the thousands of dispatching decisions made every day in a fab. Real-time resolution of tool queues, with consideration of changing equipment states, process restrictions, physical and logical location of WIP, supply chain objectives and a myriad of other parameters, is required to ensure successful dispatching in the dynamic fab environment. However, the real-time dispatching decision in semiconductor manufacturing generally remains a reactive, heuristic response in existing applications, limited to the current queue of each tool. The shortcomings of this method of assigning WIP to tools, aptly named \"opportunistic scavenging\" as stated in G. Sullivan (1987), have become more apparent in lean manufacturing environments where lower WIP levels present fewer obvious opportunities for beneficial lot sequencing or batching. Recent advancements in mixed integer programming (MIP) and constraint programming (CP) have raised the possibility of integrating optimization software, commonly used outside of the fab environment to compute optimal solutions for scheduling scenarios ranging from order fulfillment systems to crew-shift-equipment assignments, with a real-time dispatcher to create a short-interval scheduler. The goal of such a scheduler is to optimize WIP flow through various sectors of the fab by expanding the analysis beyond the current WIP queue to consider upstream and downstream flow across the entire tool group or sector. This article describes the production implementation of a short-interval local area scheduler in IBM's leading-edge 300mm fab located in East Fishkill, New York, including motivation, approach, and initial results","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122259554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
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