M. Ham, M. Raiford, F. Dillard, W. Risner, M. Knisely, J. Harrington, T. Murtha, Hyung Tae Park
{"title":"Dynamic Wet-Furnace Dispatching/Scheduling in Wafer Fab","authors":"M. Ham, M. Raiford, F. Dillard, W. Risner, M. Knisely, J. Harrington, T. Murtha, Hyung Tae Park","doi":"10.1109/ASMC.2006.1638739","DOIUrl":null,"url":null,"abstract":"The pre-cleaning equipment (or wet etch) in semiconductor manufacturing can load more than one dozen lots at one time. Because of the large capacity, the wet etch plays a key role in keeping the line balanced. After the wet etch operation, the wafers go mainly to furnaces, and the remaining goes to dry etch, CVD, photo or back to wet etch. If the wet etch produces the wafers in unbalanced fashion, the downstream equipment can be starved for inventory. Furthermore, there are often queue time restrictions between the wet etch and the downstream step and vice versa. This paper shows the success story of developing and implementing the wet etch scheduler which enables us to insure the proper inventory level at downstream steps and meet the queue time restriction at Samsung Austin Semiconductor","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2006.1638739","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
The pre-cleaning equipment (or wet etch) in semiconductor manufacturing can load more than one dozen lots at one time. Because of the large capacity, the wet etch plays a key role in keeping the line balanced. After the wet etch operation, the wafers go mainly to furnaces, and the remaining goes to dry etch, CVD, photo or back to wet etch. If the wet etch produces the wafers in unbalanced fashion, the downstream equipment can be starved for inventory. Furthermore, there are often queue time restrictions between the wet etch and the downstream step and vice versa. This paper shows the success story of developing and implementing the wet etch scheduler which enables us to insure the proper inventory level at downstream steps and meet the queue time restriction at Samsung Austin Semiconductor