深沟槽电阻和减少泄漏- 300mm工厂大批量DRAM制造中的Poly1掺杂工艺优化

Minsoo Kim, W. Cooper, B. Simonson, D. Ricks, E. McDaniel, R. Miller, R. Chapman, T. Taylor, R. Fuller
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引用次数: 1

摘要

本文研究了砷掺杂多晶硅对110 nm深沟槽DRAM产品信号裕度和节点漏电流的影响。提出了优化多晶硅物理和电学质量的方法,并讨论了快速良率学习新工艺的快速电学表征所面临的挑战。最后,简要讨论了如何将这些方法应用于其他多晶硅层和下一代器件
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Deep Trench Resistance and leakage Reduction - Poly1 Doping Process Optimization in High Volume DRAM Manufacturing for 300mm Factory
In this paper, we describe the influence of arsenic doped poly-silicon on signal margin and node leakage current of 110 nm deep trench DRAM products. Methods on optimizing both physical and electrical qualities of poly-silicon are presented and challenges of quick electrical characterization of the new process for rapid yield learning are discussed. Finally, how these methods can be applied to other poly layers and to the next generation devices are briefly discussed
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