The 17th Annual SEMI/IEEE ASMC 2006 Conference最新文献

{"title":"High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology","authors":"R. Gehres, R. Malik, R. Amos, J. Brown, S. Butt, A. Chan, C. Collins, B. Colwill, B. Davies, A. Gabor, N. Le, P. Lindo, K. Mello, E. Meyette, V. Nastasi, J. Patrick, A. Piper, D. Prakash, T. Rust, A. Santiago, T. Su, R. van Roijen, M. Rutten, D. Slisher, B. Tessier, J. Tetzloff, D. Wehella-gamage, R. Wise, Q. Yang, C. Yu, R. Divakaruni, G. Goth","doi":"10.1109/ASMC.2006.1638793","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638793","url":null,"abstract":"The ability to meet the demand for improved microprocessor performance is made difficult due to the simultaneous need not to increase power consumption. In order to meet these conflicting demands, IBM introduced a 90 nm dual stress liner CMOS technology to improve performance without increasing power consumption (Santiago et al., 2006). In IBM's 300 mm fab, this technology was introduced on multiple microprocessors, designed by different design groups with different architectures. These microprocessors, which were originally designed for a single liner technology, were optimized for systematic yield, power/performance; circuit limited yield (CLY), and random defect limited yield. The benefit of the dual stress liner technology is demonstrated in the power/performance characteristic of a dual core microprocessor and the successful technology ramp is demonstrated by yields of two microprocessors","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127320793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel Sustainable and Structured Model, System and Methodology for Engineering Competency Development","authors":"R. Ng, Sook Chien Chan, Victor Kam Kien Wong","doi":"10.1109/ASMC.2006.1638785","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638785","url":null,"abstract":"Rapid technology evolution in the semiconductor industry induces new challenges for multinational corporations to hire competent engineers for design & development related job functions. This technology movement requires hired college graduates and experienced engineers to continuously upgrade their technical knowledge in order to keep up with the pace. However, there is no established model to systematically guide the technical workforce on how to address this problem in breadth and depth. Upon conducting a site-wide needs analysis, we discovered the absence of engineering curriculum for engineers from across various divisions, departments and functions and also responsible for the design & development of multi products: microprocessor, chipset, network processor, motherboard and networking modules. This paper presents the novel technical training model, system and method in solving the problem. The model describes the engineering development curricula (EDC), the system refers to the Engineering Development Team (EDT) and the methodology describes the curricula execution by the EDT to ensure quality, sustainability and timeliness. Finally, we depict result indicators and measurements techniques","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115609084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Brightfield iADC Applications for Yield Learning and Excursion Monitoring","authors":"J. Wittenzellner","doi":"10.1109/ASMC.2006.1638752","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638752","url":null,"abstract":"Inline ADC provides classification data for all detected wafer defects at run time, without having a negative impact on tool throughput. MTV has successfully used iADC to monitor excursions as well as predict probe fails using inline inspections. The use of iADC has reduced MTV's reliance on SEM review and allowed for more consistent disposition of process issues on the production floor. While iADC is not a standalone solution to yield improvement, it does provide another powerful tool for the defect engineer","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122657392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Point-of-Use Ultra-Pure Water for Immersion Lithography","authors":"M.E. Clarke, A. Xia, J. Smith, B. Parekh","doi":"10.1109/ASMC.2006.1638751","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638751","url":null,"abstract":"In this paper we describe the design and development of point-of-use UPW (ultra pure water) components and systems for the immersion application. The paper addresses the water quality needs for the immersion lithography process and presents key contaminant removal techniques and performance results. POU water delivery systems are designed based upon individual customer needs","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124971545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Innovative Yield Modeling using Statistics","authors":"K. Anderson","doi":"10.1109/ASMC.2006.1638747","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638747","url":null,"abstract":"Yield loss in semiconductor manufacturing has been a concern since the invention of the integrated circuit by Kilby, et. al (1958). There has often been contentious disagreement in the literature on the subject of yield modeling. From a business perspective, the utility of accurately describing past yields and predicting the future yield of a product is obvious. It is arguably the single most influential metric to gauge the financial success of a product, process, and manufacturer. Unfortunately, simple models fail to accurately describe the actual mechanisms of yield loss, and models with good fidelity can be extremely complex, thus difficult to implement and sustain. Most parsimonious die yield models use the Poisson distribution as the base. It has been and is well known that certain Poisson assumptions, e.g. spatial independence of faults, are frequently and violently violated. These violations often cause systematic bias in yield estimations using these models, to the point of making the model predictions grossly inaccurate, usually in the unoptimistic direction. Yield modeling \"state-of-the-art\" now uses other distributions almost exclusively, of which the negative binomial is the most popular. The only additional term that needs definition from the previous Poisson distribution is the clustering parameter, alpha. This clustering parameter ranges from 1, which indicates a high degree of fault clustering, to infin, which indicates no clustering at all...random faults. The International Technical Roadmap for Semiconductors (2005) recommends this yield model with a clustering parameter of 2, but this value is a sweeping generalization that simplifies the model, but may or may not represent the yield of a certain process or product with acceptable fidelity. This presentation discusses studies using the negative binomial yield model with innovative spatial statistics using Markov random fields and nonlinear regression adaptations to directly estimate both D0 and a simultaneously. It discusses the coupling of statistical, mathematical, and fuzzy logic approaches to scaling those estimates to other products and technologies. These procedures can be employed to accomplish an accurate comparison of product yields, make design recommendations, and to forecast yields for products even when they have yet to be manufactured. Model fidelities and predictions have been proven very accurate. The presentation also presents an innovative approach to the prediction of yield over time that utilizes a modified logistic model, to estimate yield learning rates and quantify the speed and acceleration of yield improvements","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130138972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New Tool for Targeting Energy Improvements in Semiconductor Manufacturing Equipment","authors":"P. Naughton","doi":"10.1109/ASMC.2006.1638796","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638796","url":null,"abstract":"Resource consumption directly impacts the cost of semiconductor manufacturing and indirectly contributes to increases in global warming. Since 1996, several resource conservation projects and surveys have been performed at SEMATECH, its member companies, and semiconductor manufacturing equipment (SME) suppliers. Significant reductions in SME resource consumption are possible, but are they enough? The International Technology Roadmap for Semiconductors (ITRS) continues to challenge new fobs and SME designers to meet ever-decreasing energy goals. The World Semiconductor Council has issued their white paper on energy suggesting normalized energy reductions for wafer fabs. To achieve measurable reductions, both factory owners and SME suppliers will need to baseline their energy consumption and establish specific targets for improvement. Target setting must include the total energy requirements for process equipment, its support components (e.g., vacuum pumps, abatement devices, chillers), and all support utilities (e.g., power, water, compressed air, etc.). To measure, track, and report the progress towards improvement goals, a total equivalent energy (TEE) tool is presented. One of the key components of the TEE methods to be addressed is the use of energy conversion factors (ECFs)","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel Methods for Identification and Analysis of Various Yield Problems in Semiconductor Manufacturing","authors":"Chang Huhn Lee, Jae Yun Moon, Kyu Whan Chong, Hyung Dong Woo, Seog Hee Kang, Kyung Seok Oh, Seok Woo Hong, Jae Cheol Lee","doi":"10.1109/ASMC.2006.1638749","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638749","url":null,"abstract":"Overwhelming data is produced during semiconductor processing and it becomes more important to classify a large number of wafers into various types of failures for the root cause analysis of the yield excursion as quickly as possible. In this paper, feature vector based methods have been suggested for the classification of wafers and their application to the root cause analysis. Local bin profile has been calculated to generate a feature vector for a wafer. K-means clustering method has been used to cluster these vectors for the classification of wafers. ANOVA or Kruscal-Wallis test has been applied to one of the components of a feature vector for the yield analysis, depending on its normality. Our yield analysis examples have proven that these analysis methods are very effective and quick in pinpointing the root cause for the various types of failures, especially the equipment-originated ones, including those otherwise would be impossible with the conventional methods","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126665846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formation and Reduction of Embedded Contamination Defects Detected after FEOL Poly Patterning","authors":"Chienfan Yu, R. Arndt, P. Ronsheim, M. St. Lawrence, Hong Lin, M. Zaitz, B. Colwill, J. Bruley, G. Crispo","doi":"10.1109/ASMC.2006.4676216","DOIUrl":"https://doi.org/10.1109/ASMC.2006.4676216","url":null,"abstract":"Embedded contamination (EC) is a significant contributor to front-end-of-line (FEOL) defects detected at poly conductor (PC) bright field (BF) PLY (process limited yield) inspection after poly patterning. There are two types of EC defects found in PC PLY after poly line formation. A small percentage of them has relatively larger size than ground rule and is believed to be related to particle residue incoming to or fallen during poly silicon deposition. The vast majority of the ECs are small and appear first at post poly deposition dark field (DF) PLY inspection as poly bumps. Subsequent PC lithographic pattering and plasma etch modification transform the poly bumps into ECs as detected in PC BF PLY. No appreciable correlation of these small bumps was found to any of the prior level partition BF PLY defects through the defect source analysis (DSA). Larger EC was found to be effectively removed with improved wet clean and the use of cryogenic aerosol clean prior to well anneal process. Small EC was found to be reduced by proper control and minimization of STI height and divot, as well as the processing procedure and environment change","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130738363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"From Atoms and Molecules to Information and Knowledge: New Driving Forces in Manufacturing","authors":"E. S. Meieran","doi":"10.1109/ASMC.2006.1638766","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638766","url":null,"abstract":"In the 40 years since Gordon Moore articulated his famous Moore's Law, enormous changes have taken place in all industries and particularly in the semiconductor industry. The first decade of Moore's Law, the 60's and early 70's was dominated by semiconductor process development, which gave the world the foundation devices that now empower the world through advanced communication and computation capabilities. The second decade, the late 70's and early 80's, was dominated by computer architects, who defined the memory and microprocessor devices that led to the personal computer industry. The third decade, the mid 80's to the mid 90's, saw device design as a core competency; as the ability to link millions and tens of millions of devices to make more sophisticated circuits led to vastly more sophisticated devices. The next decade, the 90's to the present time, was dominated by manufacturing, where making these great devices by the hundreds of millions became a competitive advantage, leading to advanced computing, communication and Internet capabilities. So what's next; what will emerge from this decade? The most significant attributes of the coming generations are the introduction of ever newer, lower cost, more sophisticated devices and the opening of new markets, particularly in emerging economies; consequently, there will be a major emphasis on the manufacturing domain as pressure continues to be competitive in price, quality, performance and in particular, delivery time. This paper discusses some of the major trends that will impact manufacturing, given these competitive product pressure; it seems to me that the most significant impact will be through sharing and leveraging of manufacturing-related knowledge, as process complexity increases and the work is more globally distributed. Maybe knowledge is power, but globally distributed shared knowledge is certainly GREAT power!","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"176 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133524339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Control of Contact Hole Distortion by Using Polymer Deposition Process (PDP) for sub-65nm Technology and Beyond","authors":"Judy Wang, S. Sung, Shawming Ma","doi":"10.1109/ASMC.2006.1638728","DOIUrl":"https://doi.org/10.1109/ASMC.2006.1638728","url":null,"abstract":"Contact hole distortion in dielectric etching was investigated and it is found that the contact hole distortion is mainly caused by low mask selectivity, poor mask surface control (roughness, striation, pitting or pin hole) before and after etching. The surface roughness and mask selectivity have been studied to overcome the problem of pattern deformation of photoresist (PR) and C-rich materials as the mask. By using the polymer deposition process (PDP), the mask degradation is improved and the contact profile is well controlled. This paper focuses on the discussion of PDP chemistry selection, PDP time decision, and PDP used at before or after BARC (bottom anti-reflective coating) open step","PeriodicalId":407645,"journal":{"name":"The 17th Annual SEMI/IEEE ASMC 2006 Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132296681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}