{"title":"A method for stability compensation of low-load-capacitor low-power LDO","authors":"Sajal Kumar Mandal","doi":"10.1109/ICECS.2008.4674841","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674841","url":null,"abstract":"A stability compensation method for low-load-capacitor low dropout regulator (LDO) is presented. A ldquozeropsilas frequency trackingrdquo as well as ldquonon-dominant parasitic polespsila frequency reshapingrdquo are performed to obtain nearly first order system behavior out of several quite unmanageable locations of pole-zero frequencies of uncompensated system. The LDO consumes 170 muA (including the consumption of reference circuit) over full load current range and is implemented on 0.13 mum CMOS technology.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126991510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 65 nm CMOS - Stacked Folded Fully Differential (SFFD) PA structure for W-CDMA application","authors":"Y. Luque, N. Deltimple, E. Kerhervé, D. Belot","doi":"10.1109/ICECS.2008.4674815","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674815","url":null,"abstract":"This paper presents a 65 nm CMOS-power amplifier (PA) designed for mobile communications.The PA is based on a new structure, the stacked folded fully differential (SFFD) which is inspired by a push-pull structure. The PA is designed for the UMTS W-CDMA standard which requires linearity from -20 dBm to 24 dBm output power. The power amplifier provides 31 dBm output power with 26% of power added efficiency (PAE) at 1.95 GHz. The linear gain is 20 dB and the compression point (OCP1) is 25.6 dBm. In order to meet the UMTS W-CDMA requirements, the PA is linear until 24 dBm, which is the maximum output power required by this standard.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Specialised excitation and wavelet feature extraction in fault diagnosis of analog electronic circuits","authors":"L. Chruszczyk, J. Rutkowski","doi":"10.1109/ICECS.2008.4674836","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674836","url":null,"abstract":"This article presents design of specialised aperiodic excitation. Purpose is improvement of fault diagnosis of analog electronic circuits. The goal is enhancement of catastrophic (hard) faults location. Further improvement is achieved after utilising additional feature extraction by means of wavelet transform. Obtained results are compared to fault diagnosis without feature extraction and diagnosis with the simplest aperiodic excitation: step function.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121457134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a digital pixel image sensor array with adaptive quantization and pseudo Huffman coding","authors":"Milin Zhang, A. Bermak","doi":"10.1109/ICECS.2008.4674992","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674992","url":null,"abstract":"In this paper, adaptive quantization algorithm with pseudo Huffman coding scheme used for image compression application integrated along with a digital pixel sensor (DPS) array is proposed. The proposed pseudo Huffman coding scheme compresses the quantization results without any loss, while saving as high as half of the bits in transmitting while comparing with the number of bits required by system without such coding scheme. Simulation results show that the adaptive quantization can usually increase the PSNR results by even higher than 25%.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124144232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of elementary multi-source networks employing TCP/IP congestion control","authors":"S. Politis, P. Curran","doi":"10.1109/ICECS.2008.4674909","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674909","url":null,"abstract":"In this paper, an analysis of a discrete-time, first-principles model of a congestion control mechanism with queueing, for a simple multi-source network running TCP, is presented and the steady state behaviour is examined.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127936360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low jitter self-calibration PLL for 10Gbps SoC transmission links application","authors":"Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu","doi":"10.1109/ICECS.2008.4674971","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674971","url":null,"abstract":"A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm2.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115790699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tunable micro-machined combline resonator","authors":"M. Chatras, D. Baillargeat, P. Blondy","doi":"10.1109/ICECS.2008.4674827","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674827","url":null,"abstract":"In this paper, two main objectives were validated. The first one was to propose a new topology of micromachined tunable combline resonator around 30 GHz with 60% of tunable range. The second objective was to validate a technological process. This work was validated by RF measurements.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"348 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132499229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Construction of the cyclic block-type LDPC codes for low complexity hardware implementation","authors":"Kuang-Hao Lin, R. Chang, A. Huang, Sheng-Dong Wu","doi":"10.1109/ICECS.2008.4675071","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675071","url":null,"abstract":"In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology","authors":"Shih-Hung Chen, M. Ker","doi":"10.1109/ICECS.2008.4674941","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674941","url":null,"abstract":"NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131202691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modelling TrenchMOSFETs in SPICE","authors":"J. Zarebski, K. Górecki","doi":"10.1109/ICECS.2008.4674794","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674794","url":null,"abstract":"In the paper the isothermal model of TrenchMOSFETs offered by the producer of these devices and the electrothermal model of these devices proposed by the authors were presented. The results of the experimental verification of both the models are given as well.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133551877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}