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2008 15th IEEE International Conference on Electronics, Circuits and Systems最新文献

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Sallen-Key polyphase filter design 萨伦-基多相滤波器设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674843
M. Robens, R. Wunderlich, S. Heinen
{"title":"Sallen-Key polyphase filter design","authors":"M. Robens, R. Wunderlich, S. Heinen","doi":"10.1109/ICECS.2008.4674843","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674843","url":null,"abstract":"Present wireless receiver designs often make use of low intermediate frequency structures for signal reception. These topologies frequently apply polyphase filters for noise and image signal attenuation. When using active-RC implementations of single pole or direct synthesis structures, the number of operational amplifiers and thus power consumption becomes high. To confine the latter, a Sallen-Key based polyphase filter is presented in this paper which reduces the amplifier amount by one half. Furthermore, the system theoretic method used for circuit design is shown. Results are verified by Cadence simulation.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132628297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fast charging technique for Li-Ion battery charger 锂离子电池充电器的快速充电技术
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674929
Chia-Hsiang Lin, Chi-Lin Chen, Yu-Huei Lee, Shih-Jung Wang, C. Hsieh, Hong-Wei Huang, Ke-Horng Chen
{"title":"Fast charging technique for Li-Ion battery charger","authors":"Chia-Hsiang Lin, Chi-Lin Chen, Yu-Huei Lee, Shih-Jung Wang, C. Hsieh, Hong-Wei Huang, Ke-Horng Chen","doi":"10.1109/ICECS.2008.4674929","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674929","url":null,"abstract":"In this paper, the compensation of internal resistance of the Li-Ion battery is proposed. The requirement of fast and steady charger becomes the most important issue for power management ICs. Refer to the characteristics of the battery, how to charge the battery with adequate current and fasten the time of charging is critical to the devisers. Due to the impedance of battery pack, the energy of charger charged to cell is consumed in it partly. As a result, the efficiency of charger is reduced inevitably. The previous design has proposed a dynamic circuit for reducing time [1]. However the technique demands the external device to compensate the defeat. Thus, this paper extends the period of the CC mode to charge the battery with a faster speed. Owing to the shifting voltage on the reference voltage, the charger can delay the time that the operation mode from CC mode to CV mode. That is a fast-charging charger can be achieved by a large constant current stored in the battery during a long constant current period. Simulation results verify the success of the fast-charging technique due to the internal resistance compensation.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128908771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
A fully-integrated semicircular canal processor for an implantable vestibular prosthesis 一种用于植入前庭假体的全集成半规管处理器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674796
T. Constandinou, J. Georgiou, C. Toumazou
{"title":"A fully-integrated semicircular canal processor for an implantable vestibular prosthesis","authors":"T. Constandinou, J. Georgiou, C. Toumazou","doi":"10.1109/ICECS.2008.4674796","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674796","url":null,"abstract":"This paper presents a fully-integrated semicircular canal processor for an implantable vestibular prosthesis. The system includes the entire processing chain required from the microsensor interface, through the required biomimetic transfer characteristics, to a current-mode signal, suitable for feeding the stimulator. Using a switched-capacitor implementation, the circuit is inherently tunable, whilst maintaining low power operation and overcoming the need for off-chip components. The entire system core occupies an area of 0.23 mm2 in a commercially available 0.35 mum CMOS technology.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"56 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131399577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Realization of the third-order high-pass transfer function with real zeroes 三阶实零高通传递函数的实现
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674833
N. Stojković, Marino Franusic, M. Dozet
{"title":"Realization of the third-order high-pass transfer function with real zeroes","authors":"N. Stojković, Marino Franusic, M. Dozet","doi":"10.1109/ICECS.2008.4674833","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674833","url":null,"abstract":"The realization possibilities of the third-order high-pass transfer functions with the real zeroes are discussed. The filter structure consists the CR ladder network with only one operational amplifier (OA), what will give the low sensitivity circuit with the low power consumption. In this paper, the OA provides the signal feedforward and in that case, the transfer function contains real zeroes, both in and out of the origin of complex plane. The frequency responses and the time responses are presented as well as the sensitivity and the noise analysis. The obtained results are confirmed with the SPICE.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"09 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127311479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-glass digital-to-analog converter with gamma correction for panel data driver 玻璃上的数模转换器与面板数据驱动器的伽马校正
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674826
Tzu-Ming Wang, Yu-Hsuan Li, M. Ker
{"title":"On-glass digital-to-analog converter with gamma correction for panel data driver","authors":"Tzu-Ming Wang, Yu-Hsuan Li, M. Ker","doi":"10.1109/ICECS.2008.4674826","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674826","url":null,"abstract":"An on-glass 6-bit R-string digital-to-analog converter (DAC) with gamma correction for panel data driver is proposed. The proposed circuit, which is composed of folded R-string circuit, segmented digital decoder, and reordering decoding circuit, has been designed and fabricated in a 3-mum low-temperature poly-Si (LTPS) technology. The area of the proposed circuit is effectively reduced to about one sixth compared with the conventional one.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124402143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Linear programming based design of reconfigurable network on chip on eFPGA 基于线性规划的eFPGA片上可重构网络设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674970
Xinyu Li, O. Hammami
{"title":"Linear programming based design of reconfigurable network on chip on eFPGA","authors":"Xinyu Li, O. Hammami","doi":"10.1109/ICECS.2008.4674970","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674970","url":null,"abstract":"Multiprocessors system on chip are expected to be used for multiple applications which might exhibit distinct communication patterns. Finding a common efficient network on chip for these multiple applications might be simply impossible due to the diverging requirements. Reconfigurable network on chip is a potential solution in which the network is reconfigured before application execution in order to match the application specific requirements. Implementation of this reconfigurability might be done using eFPGA. In this paper we propose a methodology to specify the area dimension of reconfigurable eFPGA for NoC (Network on Chip). Various objective functions are used to drive out study. Experimental results show the effectiveness of our approach.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124496943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2GHz 65nm CMOS digitally-tuned BAW oscillator 2GHz 65nm CMOS数字调谐BAW振荡器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674955
Pierre Guillot, P. Philippe, C. Berland, J. Bercher
{"title":"A 2GHz 65nm CMOS digitally-tuned BAW oscillator","authors":"Pierre Guillot, P. Philippe, C. Berland, J. Bercher","doi":"10.1109/ICECS.2008.4674955","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674955","url":null,"abstract":"The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115106886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Design and fabrication of a miniaturized three-axis accelerometer for measuring heart wall motion 用于测量心壁运动的小型化三轴加速度计的设计与制造
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674824
C. Lowrie, M. Desmulliez, L. Hoff, O. Elle, E. Fosse
{"title":"Design and fabrication of a miniaturized three-axis accelerometer for measuring heart wall motion","authors":"C. Lowrie, M. Desmulliez, L. Hoff, O. Elle, E. Fosse","doi":"10.1109/ICECS.2008.4674824","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674824","url":null,"abstract":"This paper presents the design and fabrication of a silicon-based miniaturized piezoresistive three-axis accelerometer. By monitoring heart wall motion, this sensor can detect potential regional cardiac ischemia in patients who have undergone coronary artery bypass surgery. Preliminary results that have been obtained from animal studies demonstrate that the use of a commercial sensor can be applied to this application. However, it is also demonstrated that the design and manufacturing of a dedicated sensor is required for this specific application. This article explains the design requirements and technology processes used to develop such a sensor.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Adaptability in wireless sensor networks 无线传感器网络的适应性
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675089
Alessio Vecchio
{"title":"Adaptability in wireless sensor networks","authors":"Alessio Vecchio","doi":"10.1109/ICECS.2008.4675089","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675089","url":null,"abstract":"Adaptability is a key strategy in the design of effective wireless sensor networks. Communication schemes need to adapt to dynamic topologies and fluctuating traffic rates. Applications have to alter their behavior to respond to mutated necessities or to cope with environmental changes. The network, as a whole, has to tolerate the disappearance of faulting nodes or the appearance of additional ones. This paper discusses the role of adaptability through a set of case studies.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Analysis of the impact of process variations on static logic circuits versus fan-in 工艺变化对静态逻辑电路与扇入的影响分析
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674810
M. Alioto, G. Palumbo, M. Pennisi
{"title":"Analysis of the impact of process variations on static logic circuits versus fan-in","authors":"M. Alioto, G. Palumbo, M. Pennisi","doi":"10.1109/ICECS.2008.4674810","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674810","url":null,"abstract":"In this paper, the effect of process variations on the delay of CMOS static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor size. Theoretical results are useful to gain an insight into the dependence of the delay variation on design parameters. Monte Carlo simulations on a 90-nm technology were performed to validate the results.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123605133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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