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Piecewise linear curvature-compensated CMOS bandgap reference 分段线性曲率补偿CMOS带隙基准
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674852
Hong-Yi Huang, Ru-Jie Wang, Shih-Chiang Hsu
{"title":"Piecewise linear curvature-compensated CMOS bandgap reference","authors":"Hong-Yi Huang, Ru-Jie Wang, Shih-Chiang Hsu","doi":"10.1109/ICECS.2008.4674852","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674852","url":null,"abstract":"A low-voltage low-power bandgap voltage reference without using passive components is presented. Using piecewise linear curvature-compensated scheme, a reference voltage of 646.4 mV is generated with a temperature coefficient of 1.7 ppm/degC in the range [-40, +125] degC at 1.8-V supply voltage. A line sensitivity of 0.18 mV/V in the supply voltage range [+1, +1.8] V is achieved. It dissipates a maximum power of 4.4 muW at a 1.8-V supply voltage and 125 degC. The silicon area is 100 times 50 mum2 in 0.18um CMOS process.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133425080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Effects of the previous pulse shift and filter on the symbol synchronizer PLL 先前脉冲移位和滤波器对符号同步器锁相环的影响
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675028
A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho
{"title":"Effects of the previous pulse shift and filter on the symbol synchronizer PLL","authors":"A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho","doi":"10.1109/ICECS.2008.4675028","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675028","url":null,"abstract":"We will study the effects of the shift of the previous pulse temporal position (between P1 and P2) on the symbol synchronizers jitter behavior. Each pulse temporal position (P1 and P2), with the same previous filter, forms a group with four different carrier PLL (phase lock loop) namely the analog, hybrid, combinational and sequential. The main objective is to study the synchronizers output jitter UIRMS (unit interval root mean squared) as function of the input SNR (signal to noise ratio).","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122498973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS bulk input current switch logic circuit CMOS批量输入电流开关逻辑电路
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674899
Hong-Yi Huang, C. Hung, Sheng-Chia Chiang
{"title":"CMOS bulk input current switch logic circuit","authors":"Hong-Yi Huang, C. Hung, Sheng-Chia Chiang","doi":"10.1109/ICECS.2008.4674899","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674899","url":null,"abstract":"In this work, the CMOS bulk-input current switch logic (BCSL) circuit is proposed. A negative (positive) boost circuit providing a voltage level for NMOS (PMOS) bulk terminal is also developed to avoid the forward biasing of drain/source-to-bulk junctions. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to low parasitic resistive and capacitive load. The dynamic power is reduced. The BCSL has the potential of low-power and high-speed operation in low-voltage design. It is shown that the BCSL has better speed and power performance compared to the conventional differential logic circuits in simulation results.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"43 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122943901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VLSI network of spiking neurons with plastic fully configurable “stop-learning” synapses 一个由尖峰神经元组成的超大规模集成电路网络，具有可塑的、完全可配置的“停止学习”突触
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674944
M. Giulioni, Patrick Camilleri, V. Dante, D. Badoni, G. Indiveri, J. Braun, P. D. Giudice
{"title":"A VLSI network of spiking neurons with plastic fully configurable “stop-learning” synapses","authors":"M. Giulioni, Patrick Camilleri, V. Dante, D. Badoni, G. Indiveri, J. Braun, P. D. Giudice","doi":"10.1109/ICECS.2008.4674944","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674944","url":null,"abstract":"We describe and demonstrate a neuromorphic, analog VLSI chip (termed F-LANN) hosting 128 integrate-and-fire (IF) neurons with spike-frequency adaptation, and 16,384 plastic bistable synapses implementing a self-regulated form of Hebbian, spike-driven, stochastic plasticity. The chip is designed to offer a high degree of reconfigurability: each synapse may be individually configured at any time to be either excitatory or inhibitory and to receive either recurrent input from an on-chip neuron or AER-based input from an off-chip neuron. The initial state of each synapse can be set as potentiated or depressed, and the state of each synapse can be read and stored on a computer.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123059979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Shaping of bidimensional distributed structures 二维分布结构的塑造
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674862
A. Manolescu, A. Manolescu
{"title":"Shaping of bidimensional distributed structures","authors":"A. Manolescu, A. Manolescu","doi":"10.1109/ICECS.2008.4674862","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674862","url":null,"abstract":"In this paper we present some results obtained in the study of themain properties of bidimensional distributed microelectronic structures with emphasis on the importance of shape in determining the behavior of the structure. Although these properties are illustrated using examples of resistive structures, the principal aspects based on their bidimensionality are of general utility. Some important results obtained for improving the manufacturability and the robustness of a design or for optimizing the aspect of the electrical field spectrum are presented and explained.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123068482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
AER and dynamic systems co-simulation over Simulink with Xilinx System Generator 利用Xilinx System Generator在Simulink上进行AER和动态系统联合仿真
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675094
A. Jiménez-Fernandez, A. Linares-Barranco, R. Paz-Vicente, Carlos Daniel Luján-Martínez, G. Jiménez-Moreno, A. C. Balcells
{"title":"AER and dynamic systems co-simulation over Simulink with Xilinx System Generator","authors":"A. Jiménez-Fernandez, A. Linares-Barranco, R. Paz-Vicente, Carlos Daniel Luján-Martínez, G. Jiménez-Moreno, A. C. Balcells","doi":"10.1109/ICECS.2008.4675094","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675094","url":null,"abstract":"Address-event representation (AER) is a neuromorphic communication protocol for transferring information of spiking neurons implemented into VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, what makes possible the development of complex, multilayer, multichip neuromorphic systems. In biology one of the last steps of the processing is to move a muscle, to apply the results of these complex neuromorphic processing to the real world. One interesting question is to be able to transform, or translate, the AER information into robot movements, like for example, moving a DC motor. This paper presents several ways to translate AER spikes into DC motor power, and to control a DC motor speed, based on Pulse Frequency Modulation. These methods have been simulated into Simulink with Xilinx system generator, and tested into the AER-Robot platform.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127912893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias 采用自适应体偏置的基于CML电路的2.64GHz宽范围低功耗dll倍频器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674972
Chih-Hsing Lin, C. Chiu
{"title":"A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias","authors":"Chih-Hsing Lin, C. Chiu","doi":"10.1109/ICECS.2008.4674972","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674972","url":null,"abstract":"A wide-range, low-power delay-locked loop based (DLL-based) frequency multiplier with the PMOS active load and adaptive body biasing (ABB) circuit is proposed. Adding the PMOS active load in the delay cells has the inductive-peaking effect to increase the operation frequency range. With the clocked-power ABB current mode logic (CML) exclusive-OR (XOR) circuit, the frequency multiplier can achieve power saving to 54.9% compared with convention CML XOR circuits. This is achieved by reducing the supply voltage to 1 V and dc-level of the differential inputs, while maintaining the original swing of differential outputs. The frequency multiplier can generate N times of frequency of the input clock when the number of delay cells (N) in the voltage control delay line (VCDL) is even. The proposed DLL-based frequency multiplier can operate from 80 MHz to 2.64 GHz using 0.18 mum CMOS process. The measured peak-to-peak jitters of the DLL core are 30.56 ps at 330 MHz and 70 ps at 80 MHz. The power consumption and jitter of the proposed frequency multiplier at 2.64 GHz are 27.79 mW and 23.5 ps, respectively.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128723206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache DLX HOTOKADA:具有单级缓存的32位双核DLX微处理器的设计和实现
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674891
Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, J. V. Zarsuela, A. Ballesil, J. Reyes
{"title":"DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache","authors":"Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, J. V. Zarsuela, A. Ballesil, J. Reyes","doi":"10.1109/ICECS.2008.4674891","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674891","url":null,"abstract":"Data access in main memory units can be sufficient for processors but due to demands for faster computers nowadays, implementation of multiple cores as well as the usage of a cache to increase performance, are necessary. These two solutions were implemented using a 32-bit pipelined DLX microprocessor, resulting to a dual core capable (DCC) DLX with single-level cache in a Uniform Memory Access Architecture type. This project made use of the Shared Cache System divided into an Instruction Cache and a Data Cache to solve processor structural hazards due to coincident instruction and data access.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116397647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of a small area and low power CMOS D/A converter based on the Alpha-Power Law MOSFET model 基于幂律MOSFET模型的小面积低功耗CMOS D/ a变换器设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674840
Dae-Jung Kim, Sanghoon Hwang, Heewon Kang, Seungjin Yeo, Dubok Lee, Junho Moon, Minkyu Song
{"title":"Design of a small area and low power CMOS D/A converter based on the Alpha-Power Law MOSFET model","authors":"Dae-Jung Kim, Sanghoon Hwang, Heewon Kang, Seungjin Yeo, Dubok Lee, Junho Moon, Minkyu Song","doi":"10.1109/ICECS.2008.4674840","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674840","url":null,"abstract":"While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the Alpha-Power Law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100MSPS CMOS current steering Digital-to-Analog Converter (DAC) with the Alpha-Power Law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control-switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8 V, 0.18 mum, 1-poly, 5-metal CMOS technology. It occupies 0.52 mm2 of silicon area with 15.8 mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal-driven white space redistribution for block-level floorplans 热驱动的白色空间重新分配为块级平面图
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674940
Jin-Tai Yan, Zhi-Wei Chen, Y. Chou, Shun-Hua Lin, H. Chiueh
{"title":"Thermal-driven white space redistribution for block-level floorplans","authors":"Jin-Tai Yan, Zhi-Wei Chen, Y. Chou, Shun-Hua Lin, H. Chiueh","doi":"10.1109/ICECS.2008.4674940","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674940","url":null,"abstract":"Given an LB-compact floorplan, a 3D block-level thermal model is firstly proposed to calculate the temperature of each circuit block in reasonable time. Furthermore, based on the temperature calculation in the proposed 3D block-level thermal model and the final floorplan region, an iterative approach is proposed to reduce the final floorplan temperature by inserting or redistribution the feasible white space. The experimental results show that our proposed iterative approach obtains very promising temperature reduction in reasonable CPU time for MCNC benchmarks.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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