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2008 15th IEEE International Conference on Electronics, Circuits and Systems最新文献

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C-based hardware-accelerator coprocessing for SOC an quantitative area-performance evaluation 基于c的SOC硬件加速器协同处理与定量面积性能评估
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674905
Zhoukun Wang, O. Hammami
{"title":"C-based hardware-accelerator coprocessing for SOC an quantitative area-performance evaluation","authors":"Zhoukun Wang, O. Hammami","doi":"10.1109/ICECS.2008.4674905","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674905","url":null,"abstract":"C-based hardware-accelerated embedded system has been proposed to tackle the increasing time-to-market pressure and the growing complexity of system on chip (SoC). Due to tools selection and different set of synthesis, place and route options, numerous low level solutions in term of area and frequency can be produced and must be considered in high abstraction level. In this paper we conduct a quantitative area-performance evaluation of C-based high level synthesis of hardware-accelerator co-processing. Several experimental results are presented to show the impact of various C-based synthesis tools (systemC Agility, impluseC) and the impact of option selections in the context of complete SOC environment.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115369551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Permanent-magnet wind turbines control tuning and torque estimation improvements 永磁风力涡轮机控制调谐和转矩估计改进
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674960
E. Robles, S. Ceballos, J. Pou, A. Arias, J. L. Martín, P. Ibañez
{"title":"Permanent-magnet wind turbines control tuning and torque estimation improvements","authors":"E. Robles, S. Ceballos, J. Pou, A. Arias, J. L. Martín, P. Ibañez","doi":"10.1109/ICECS.2008.4674960","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674960","url":null,"abstract":"This paper presents and discuses different PI tuning methods and control strategies for a permanent magnet synchronous machine. The machine is a part of a wind turbine generation system in which two back-to-back-connected three-level converters are the power interface to the electrical grid. It is demonstrated that, for the speed control loop, the zero-pole cancellation method does not provide good performance to the system. Therefore, the PI regulator should be tuned using other strategies. Furthermore, a torque estimator is included in the speed control loop which practically avoids any transient process due to wind torque disturbances. The results are experimentally verified in a laboratory prototype.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115645115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A novel baseline holder circuit for nuclear imaging front-end electronics 一种新型核成像前端电子学基线保持电路
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674947
F. Corsi, M. Foresta, C. Marzocca, G. Matarrese, A. Tauro
{"title":"A novel baseline holder circuit for nuclear imaging front-end electronics","authors":"F. Corsi, M. Foresta, C. Marzocca, G. Matarrese, A. Tauro","doi":"10.1109/ICECS.2008.4674947","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674947","url":null,"abstract":"A novel baseline holder circuit (BLH) is proposed here, able to produce a stable baseline level at the output of a typical analog front-end channel for particle detectors, both at dc and at high rate operation. The circuit is suitable to be used in modern high-sensitivity gamma-ray medical imaging systems, where high gain shapers are required. A very low frequency pole, which is fundamental for the stability of the shaper-BLH loop, is realized by means of operational transconductance amplifiers (OTA), which allow to save area, making the circuit suitable for the integration in a standard CMOS technology. Non-linearity effects have been exploited to reduce the baseline shift at high input signal rates, due to the low dc gain of the shaper+BLH system. The circuit has been designed in a standard 0.35 mum CMOS technology, and extensive simulations prove the effectiveness of the adopted solutions. A baseline drift of less than 1.8 mV has been observed for a 30 KHz input rate.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114658897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A design method for separable-denominator 2D IIR filters using a stability criterion based on the system matrix 一种基于系统矩阵的可分分母二维IIR滤波器的稳定性准则设计方法
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674981
T. Miyata, N. Aikawa, Y. Sugita, T. Yoshikawa
{"title":"A design method for separable-denominator 2D IIR filters using a stability criterion based on the system matrix","authors":"T. Miyata, N. Aikawa, Y. Sugita, T. Yoshikawa","doi":"10.1109/ICECS.2008.4674981","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674981","url":null,"abstract":"In this paper, we propose designing method for separable-denominator two-dimensional Infinite Impulse Response (IIR) filters (separable 2D IIR filters) by Successive Projection (SP) methods using a stability criterion based on the system matrix. It is generally known that separable 2D IIR filters are stable if and only if each of the denominators is stable. Therefore, the stability criteria of 1D IIR filters can be used for separable 2D IIR filters. A stability criterion based on the system matrix is a necessary and sufficient condition to guarantee stability in 1D IIR filters. Therefore, separable 2D IIR filters obtained by the proposed method have a smaller error ripple than those obtained by the conventional method.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124841872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Efficient parallel processing algorithm for fast calculation of 3D filtering using the VR FHT 利用VR FHT快速计算三维滤波的高效并行处理算法
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674985
M. Aziz
{"title":"Efficient parallel processing algorithm for fast calculation of 3D filtering using the VR FHT","authors":"M. Aziz","doi":"10.1109/ICECS.2008.4674985","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674985","url":null,"abstract":"in this paper we present an efficient and adaptable three dimensional (3D) parallel filtering algorithm based on the fast 3-D vector-radix fast Hartley transform (3-D VR FHT). This algorithm is suitable for high resolution / high speed multidimensional signal and video processing. The 3-D parallel algorithm is highly efficient as it solves the problems of computations overhead and performance limitations associated with the block filtering method by eliminating the overlapping segments and boundary conditions in the parallel filter structure. It also lifts the restrictions on the input size for high performance, as both the 3-D input data and impulse response of the system are segmented into smaller subsections. These subsections are independent and can be simultaneously processed. The algorithmpsilas structure and mathematical derivation are given and the performance of the algorithm is tested on a real multiprocessor parallel system.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124908552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A two-bit-per-cycle successive-approximation ADC with background offset calibration 具有背景偏移校准的每周期2位连续逼近ADC
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674937
Michele Casubolo, M. Grassi, A. Lombardi, F. Maloberti, P. Malcovati
{"title":"A two-bit-per-cycle successive-approximation ADC with background offset calibration","authors":"Michele Casubolo, M. Grassi, A. Lombardi, F. Maloberti, P. Malcovati","doi":"10.1109/ICECS.2008.4674937","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674937","url":null,"abstract":"In this paper we present a 10-bit, two-bit per cycles successive-approximation A/D converter (ADC). The circuit, operated at 60 MHz clock frequency, achieves a sampling frequency of 10 MHz, requiring only 6 clock cycles to accomplish a conversion. The ADC exploits three comparators to resolve two bits during each conversion cycle. To avoid the severe performance degradation due to offset mismatches among the comparators, we developed a novel background offset calibration technique. During the input signal sampling phase, when the comparators would otherwise be idle, we reconfigure the circuit to implement three one-bit per cycle, 8-bit successive-approximation ADCs, which within 8 conversion cycles measure the offset of each comparator. The effect of the comparator offset is then canceled in the digital domain. Simulation results confirm the effectiveness of the proposed solution, allowing to achieve 10 bits of resolutions even in the presence of large offsets in the comparators.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125826204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The effect of filter type on BER of WCDMA-UMTS mobile radio systems 滤波器类型对WCDMA-UMTS移动无线电系统误码率的影响
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675016
C. Kikkert
{"title":"The effect of filter type on BER of WCDMA-UMTS mobile radio systems","authors":"C. Kikkert","doi":"10.1109/ICECS.2008.4675016","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675016","url":null,"abstract":"This paper investigates the Bit Error Rates (BER) obtained using different filter types for RF front ends for WCDMA-UMTS mobile radio systems. Most Base Stations use Chebychev or Cauer-Chebychev filters. This paper compares the use of Bessel, Butterworth and Chebychev filters for use as single channel filters in a WCDMA-UMTS radio system. It is shown that even though Bessel filters pass more adjacent channel interference, they result in a significantly lower Bit Error Rate (BER) and insertion loss than the other filter types.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125924017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Synthesis of bandpass circulator-tree wave digital filters 带通环树波数字滤波器的合成
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674983
L. Wanhammar, B. Soltanian, O. Gustafsson, K. Johansson
{"title":"Synthesis of bandpass circulator-tree wave digital filters","authors":"L. Wanhammar, B. Soltanian, O. Gustafsson, K. Johansson","doi":"10.1109/ICECS.2008.4674983","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674983","url":null,"abstract":"In this paper, we discuss the design of bandpass circulator-tree wave digital filters derived from analog lowpass filters using the geometrical symmetric transformation. These structures are an interesting alternative to lattice WDFs showing a high modularity and posses the same properties as other WDF structures.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126036488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Synchronizers based on carrier phase lock Loop and on symbol phase lock loop 基于载波锁相环和基于符号锁相环的同步器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674845
A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho
{"title":"Synchronizers based on carrier phase lock Loop and on symbol phase lock loop","authors":"A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho","doi":"10.1109/ICECS.2008.4674845","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674845","url":null,"abstract":"The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential. The objective is to study the various synchronizers output jitter UIRMS (unit interval root mean squared) as function of the input SNR (Signal to Noise Ratio).","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bi-directional Current-Starved Pseudo Floating-Gate differentiator / integrator 双向缺流伪浮门微分器/积分器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674844
M. Azadmehr, Y. Berg, O. Mirmotahari
{"title":"Bi-directional Current-Starved Pseudo Floating-Gate differentiator / integrator","authors":"M. Azadmehr, Y. Berg, O. Mirmotahari","doi":"10.1109/ICECS.2008.4674844","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674844","url":null,"abstract":"In this paper we show how a simple Current-Starved Pseudo Floating-Gate (CSPFG) inverter can be used to realize bi-directional Circuits. The direction of the signal through the inverter is reversed (the input becomes output and vise versa) by swapping vdd and gnd, without adding any extra amplifier or circuitry. This is possible because of the symmetry of the CSPFG inverters. We use the bi-directionality property of the inverter to realize a bi-directional CSPFG Differentiator/integrator. Typical applications are in filter design and IO ports in ICs. Linearity and AC simulations are presented to show the good properties and versatility suited for Bi-directional analog circuit design.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123687723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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