C-based hardware-accelerator coprocessing for SOC an quantitative area-performance evaluation

Abstract

C-based hardware-accelerated embedded system has been proposed to tackle the increasing time-to-market pressure and the growing complexity of system on chip (SoC). Due to tools selection and different set of synthesis, place and route options, numerous low level solutions in term of area and frequency can be produced and must be considered in high abstraction level. In this paper we conduct a quantitative area-performance evaluation of C-based high level synthesis of hardware-accelerator co-processing. Several experimental results are presented to show the impact of various C-based synthesis tools (systemC Agility, impluseC) and the impact of option selections in the context of complete SOC environment.