CMOS bulk input current switch logic circuit

Abstract

In this work, the CMOS bulk-input current switch logic (BCSL) circuit is proposed. A negative (positive) boost circuit providing a voltage level for NMOS (PMOS) bulk terminal is also developed to avoid the forward biasing of drain/source-to-bulk junctions. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to low parasitic resistive and capacitive load. The dynamic power is reduced. The BCSL has the potential of low-power and high-speed operation in low-voltage design. It is shown that the BCSL has better speed and power performance compared to the conventional differential logic circuits in simulation results.