Thermal-driven white space redistribution for block-level floorplans

Abstract

Given an LB-compact floorplan, a 3D block-level thermal model is firstly proposed to calculate the temperature of each circuit block in reasonable time. Furthermore, based on the temperature calculation in the proposed 3D block-level thermal model and the final floorplan region, an iterative approach is proposed to reduce the final floorplan temperature by inserting or redistribution the feasible white space. The experimental results show that our proposed iterative approach obtains very promising temperature reduction in reasonable CPU time for MCNC benchmarks.