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2008 15th IEEE International Conference on Electronics, Circuits and Systems最新文献

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The impact of dielectric relaxation on ΣΔ-modulators 介电松弛对ΣΔ-modulators的影响
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675079
J. D. Maeyer
{"title":"The impact of dielectric relaxation on ΣΔ-modulators","authors":"J. D. Maeyer","doi":"10.1109/ICECS.2008.4675079","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675079","url":null,"abstract":"This paper studies the impact of dielectric relaxation on SigmaDelta-modulators. Unlike the impact on SAR and pipeline ADCs, there seems to be no research reporting on the impact of the phenomenon on SigmaDelta-modulators. Nevertheless, the SC-integrators used in the circuit implementation of SigmaDelta-modulators too rely on the transfer of charge from one capacitor to another. So, there could be an important impact of dielectric relaxation on the performance of the SC-integrator and as such on the complete SigmaDelta-modulators. In this paper, we will show via simulations on a test case that SigmaDelta-modulators are in fact (quite) robust against the parasitic effect of dielectric relaxation. This result will be explained with a theoretical analysis of the phenomenon.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125867250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Coherence modulation of light for mathematical operations 用于数学运算的光的相干调制
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674994
Sonia Elwardi, M. Zghal, B. Benkelfat
{"title":"Coherence modulation of light for mathematical operations","authors":"Sonia Elwardi, M. Zghal, B. Benkelfat","doi":"10.1109/ICECS.2008.4674994","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674994","url":null,"abstract":"We describe an experiment in which several analog signals are processed through a single light beam. This experiment is based on coherence modulation of light which consists in introducing optical delays, greater than the coherence length of the source, between light fields. Our experimental results are successfully compared to the numerical ones for subtraction and addition of sine and square signals.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127162720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Digital implementation of cellular neural networks 细胞神经网络的数字化实现
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674952
Ryan Grech, E. Gatt, I. Grech, J. Micallef
{"title":"Digital implementation of cellular neural networks","authors":"Ryan Grech, E. Gatt, I. Grech, J. Micallef","doi":"10.1109/ICECS.2008.4674952","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674952","url":null,"abstract":"This paper presents a digital cellular neural network (CNN) for digital image processing applications. The CNN is a relatively new field in this research, making use of a high degree of parallelism to achieve higher levels of processing power which continuously paves new ways of how problems can be tackled. A digital architecture is employed due to the fact that digital devices allow for a very robust, yet simple and modular design while at the same time maintaining established performance standards. Digital design was carried out with VHDL using an iterative design methodology, meaning that only one out of several building blocks are chosen to ensure optimality, robustness and operational correctness. The main design objectives were to construct a digital CNN architecture which is fast and compact for digital image processing applications like next generation digital cameras.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130066829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Bang-bang CDR circuits with equations of linear motion 用线性运动方程分析Bang-bang CDR电路
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675060
Archit Joshi
{"title":"Analysis of Bang-bang CDR circuits with equations of linear motion","authors":"Archit Joshi","doi":"10.1109/ICECS.2008.4675060","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675060","url":null,"abstract":"This paper presents the timing analysis of a phase locked loop based clock and data recovery (CDR) circuit with Bang-bang phase detector using equations of linear motion. The stability conditions are derived in near lock and in locked states. Effect of mismatch in pull-up and pull-down currents is also analyzed during phase locking.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132073593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree 使用Baugh-Wooley算法和HPM约简树的高速和低功耗乘法器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674784
Magnus Själander, P. Larsson-Edefors
{"title":"High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree","authors":"Magnus Själander, P. Larsson-Edefors","doi":"10.1109/ICECS.2008.4674784","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674784","url":null,"abstract":"The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly improved multiplier performance. In designs based on reduction trees with logarithmic logic depth, however, the reduced number of partial products has a limited impact on overall performance. The Baugh-Wooley algorithm is a different scheme for signed multiplication, but is not so widely adopted because it may be complicated to deploy on irregular reduction trees. We use the Baugh-Wooley algorithm in our High Performance Multiplier (HPM) tree, which combines a regular layout with a logarithmic logic depth. We show for a range of operator bit-widths that, when implemented in 130-nm and 65-nm process technologies, the Baugh-Wooley multipliers exhibit comparable delay, less power dissipation and smaller area foot-print than modified-Booth multipliers.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129040892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
A clock boosting scheme for low voltage circuits 一种用于低压电路的时钟增强方案
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674781
A. Behradfar, S. Zeinolabedinzadeh, K. Hajsadeghi
{"title":"A clock boosting scheme for low voltage circuits","authors":"A. Behradfar, S. Zeinolabedinzadeh, K. Hajsadeghi","doi":"10.1109/ICECS.2008.4674781","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674781","url":null,"abstract":"Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128765472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Digital gain balancing technique for sensitive detection of minor gas concentrations 微量气体浓度敏感检测的数字增益平衡技术
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674989
S. Pal, P. Wright, H. McCann
{"title":"Digital gain balancing technique for sensitive detection of minor gas concentrations","authors":"S. Pal, P. Wright, H. McCann","doi":"10.1109/ICECS.2008.4674989","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674989","url":null,"abstract":"Ultra-sensitive detection of minor species is important in many fields. The requirement of direct online measurement of gas species in process engineering motivates fast measurements over short pathlengths. The resulting high bandwidth and low absorptions reduce the measurement Signal-to-Noise Ratio (SNR). Our target is to detect CO in engine exhaust with sensitivity of the order of 0.05 ppm-m at several kHz. In this paper, a novel electronic scheme is discussed and presented with simulation results. A generic approach is followed, to use it with either a pulsed or a continuous wave (CW) laser source. A detailed noise analysis is presented for improved understanding of the SNR of the overall scheme.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123151546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
UWB microwave chaotic oscillators based on microchip amplifiers 基于微芯片放大器的超宽带微波混沌振荡器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675010
A. Panas, E. Efremova, B. Kyarginsky, Artyom Nickishov
{"title":"UWB microwave chaotic oscillators based on microchip amplifiers","authors":"A. Panas, E. Efremova, B. Kyarginsky, Artyom Nickishov","doi":"10.1109/ICECS.2008.4675010","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675010","url":null,"abstract":"Much interest to ultra-wideband (UWB) signals stimulates development of effective sources of UWB signals. Chaotic oscillators can play the role of such sources. This report is devoted to chaotic oscillators in microwave range. Oscillator structure, simulation and experimental results are considered. Generator testbed for UWB transceiver based on the proposed oscillators is demonstrated.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114166388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reseeding using compaction of pre-generated LFSR sub-sequences 利用预先生成的LFSR子序列的压缩重新播种
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675096
A. Jutman, I. Aleksejev, J. Raik, R. Ubar
{"title":"Reseeding using compaction of pre-generated LFSR sub-sequences","authors":"A. Jutman, I. Aleksejev, J. Raik, R. Ubar","doi":"10.1109/ICECS.2008.4675096","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675096","url":null,"abstract":"Built-In Self-Test (BIST) techniques are often based on pseudo-random pattern generators, which represent simple structures that can generate necessary test stimuli for a device under test (DUT). For some designs, however, additional measures of fault coverage improvement have to be applied. LFSR reseeding is a popular technique due to its ability to considerably improve both the fault coverage and test application time by embedding specific vectors into the pseudorandom sequence. Proper selection of LFSR seeds is the key aspect in a successful reseeding scheme. In this paper, we present our approach to reseeding optimization that is based on compaction of pre-generated LFSR sub-sequences in order to select a minimal subset of to be included into the final solution. The proposed approach relies on the branch-and-bound search technique, which can provide the optimal compaction for a given test setup. Alternatively, it can run for a limited time in a heuristic mode, producing intermediate results. Experiments show that applied heuristics can yield optimal or quasi-optimal solutions in polynomial time. These solutions outperform previously published results for a similar reseeding approach.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116076073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra low voltage and, nor and XOR CMOS gates 超低电压和、非和异或CMOS门
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674986
Y. Berg, O. Mirmotahari, S. Aunet
{"title":"Ultra low voltage and, nor and XOR CMOS gates","authors":"Y. Berg, O. Mirmotahari, S. Aunet","doi":"10.1109/ICECS.2008.4674986","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674986","url":null,"abstract":"In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"275 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116214629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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