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2008 15th IEEE International Conference on Electronics, Circuits and Systems最新文献

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Testing content addressable memories using instructions and march-like algorithms 使用指令和行军算法测试内容可寻址存储器
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674968
Ma Lin, Chen Yunji, Su Menghao, Qi Zichu, Zhang Heng, Hu Weiwu
{"title":"Testing content addressable memories using instructions and march-like algorithms","authors":"Ma Lin, Chen Yunji, Su Menghao, Qi Zichu, Zhang Heng, Hu Weiwu","doi":"10.1109/ICECS.2008.4674968","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674968","url":null,"abstract":"CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where N is the number of words of the CAM and L is the width of a word. The algorithm covers 100% targeted faults. Instruction-level test using the algorithm has not any test cost on area and performance. Moreover the algorithm can be used in BIST approaches and have less performance lost for microprocessors. The paper instances the algorithm in a MIPS compatible microprocessor and have good results.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116677951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Constant multiplier design using specialized bit pattern adders 使用专用位模式加法器的常数乘法器设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674786
Kyung-Ju Cho, Suhyun Jo, Yong-Eun Kim, Yinan Xu, Jin-Gyun Chung
{"title":"Constant multiplier design using specialized bit pattern adders","authors":"Kyung-Ju Cho, Suhyun Jo, Yong-Eun Kim, Yinan Xu, Jin-Gyun Chung","doi":"10.1109/ICECS.2008.4674786","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674786","url":null,"abstract":"The problem of efficient hardware implementation of multiple constant multiplication (MCM) is encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements in area and power consumption. In this paper, we present efficient implementation method of two common subexpressions (101, 101) in canonic signed digit (CSD) representation. By Synopsys simulations of a radix-24 FFT example, it is shown that the area, speed and power consumption can be reduced up to 21%, 11% and 12%, respectively, by the proposed algorithm.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116686673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-power signal acquisition for galileo satellite navigation system 伽利略卫星导航系统的低功耗信号采集
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674923
T. Partanen, H. Sorokin, J. Takala
{"title":"Low-power signal acquisition for galileo satellite navigation system","authors":"T. Partanen, H. Sorokin, J. Takala","doi":"10.1109/ICECS.2008.4674923","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674923","url":null,"abstract":"In satellite navigation systems based on code division multiple access, the signal acquisition in receiver is a computationally intensive task where the received signal is correlated with long pseudo random noise codes. In this paper, a novel architecture for acquisition of signals with binary offset modulation is proposed. The architecture is modular and has low power consumption due to word-parallel correlation structure.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124956281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Field programmable analog array based on CMOS CFOA and its application 基于CMOS CFOA的现场可编程模拟阵列及其应用
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675035
A. Madian, S. Mahmoud, A. Soliman
{"title":"Field programmable analog array based on CMOS CFOA and its application","authors":"A. Madian, S. Mahmoud, A. Soliman","doi":"10.1109/ICECS.2008.4675035","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675035","url":null,"abstract":"A proposed configurable analog block (CAB) is presented, simulated and analyzed. The CAB consists of a CMOS current feedback operational amplifier (CFOA), presented by the authors, as the main active block, programmable resistor array, programmable capacitor array and MOSFET switches. Using the CABs, the universal field programmable analog array (FPAA) has been constructed, which can realize many signal-processing functions including variable gain amplifiers, filters. The core of the chip is occupied by an array of 16 (four by four) CAB cells. Each of these CABspsila are identical and each may communicate with any other in the array via field programmable interconnect. The input and output pins are provided around the chip and each contains a single operational amplifier, which may drive onto or off the chip. To show the reliability of the proposed CAB, different filter structures responses have been realized using the proposed CAB.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121504875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Single input multiple output universal biquad using current mirrors 单输入多输出通用biquad使用电流镜
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675031
C. Laoudias, C. Psychalinos
{"title":"Single input multiple output universal biquad using current mirrors","authors":"C. Laoudias, C. Psychalinos","doi":"10.1109/ICECS.2008.4675031","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675031","url":null,"abstract":"A novel single-input second-order multifunction filter realized by employing current mirrors is introduced in this manuscript. The proposed topology offers simultaneously the lowpass, highpass, bandpass, and bandstop frequency responses. Other attractive characteristics are its potential for low-voltage operation and the electronic tuning. In addition, the only passive elements used for realizing the multifunction filters are grounded capacitors. The filter topology could become universal by employing additional circuitry. Simulation results confirm the correct operation of the proposed structure.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125208817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis 基于非线性分析的4倍LC注入锁定分频器设计方法
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675059
S. Daneshgar, Michael Peter Kennedy
{"title":"Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis","authors":"S. Daneshgar, Michael Peter Kennedy","doi":"10.1109/ICECS.2008.4675059","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675059","url":null,"abstract":"One significant source of power consumption in modern frequency synthesizers at high frequencies is the prescaler block. In order to tackle this problem, analog injection-locked frequency dividers (ILFDs) have been considered rather than conventional digital prescalers. In recent years, diverse and sometimes contradictory algorithms for estimating the locking range in these dividers have been proposed. In this paper, we propose a new method based on nonlinear analysis to design a typical (LC oscillator-based) injection-locked frequency divider and to predict its locking range. In order to support our analysis, we design a divide-by-4 circuit and compare its simulated locking range with theoretical predictions.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"27 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113973227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 32-bit carry lookahead adder design using complementary all-N-transistor logic 采用互补全n晶体管逻辑的32位进位前瞻加法器设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674951
G. Sung, Chun-Ying Juan, Chua-Chin Wang
{"title":"A 32-bit carry lookahead adder design using complementary all-N-transistor logic","authors":"G. Sung, Chun-Ying Juan, Chua-Chin Wang","doi":"10.1109/ICECS.2008.4674951","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674951","url":null,"abstract":"A complementary all-N-transistor (CANT) comprising the ANT logic and a novel inverted ANT logic is proposed in this paper. The threshold voltage of the transistors in the ANT logicpsilas N-block is variable depending upon the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-block is raised to VDD - Vthn such that the drain current therein is increased to enhance operation speed. In the pre-charge phase, the bulk voltage of those transistors in the N-block is reduced to its normal voltage level such that the subthreshold leakage current is dropped to reduce power consumption. By utilizing such a variable bulk voltage scheme in the CANT, a 32-bit CLA is designed to justify the low power and high speed performance. The power dissipation is 143 mW at 5.4 GHz clock rate given the worst PVT (SS, 1.08 V, 75degC) condition.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131162523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On-chip supply current monitoring units using magnetic force sensing 片上供电电流监测单元采用磁力传感
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675081
M. Donoval, M. Daricek, V. Stopjaková, J. Marek
{"title":"On-chip supply current monitoring units using magnetic force sensing","authors":"M. Donoval, M. Daricek, V. Stopjaková, J. Marek","doi":"10.1109/ICECS.2008.4675081","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675081","url":null,"abstract":"A built-in on-chip current sensors design based on magnetic force of is presented. The proposed sensors are aimed to be used for on-chip current testing in deep-submicron circuits with ultra low-voltage power supply. The advantage of the proposed monitors is mainly elimination of the undesired supply voltage reduction, commonly created by standard current test methods. Description of different sensor architectures, their designs and physical implementations on chip are presented. All the sensor versions were designed in 1.0 mum BiCMOS technology.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131647711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Protecting designs with a passive thermal tag 使用被动热标签保护设计
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4674830
Carol Marsh, T. Kean, D. McLaren
{"title":"Protecting designs with a passive thermal tag","authors":"Carol Marsh, T. Kean, D. McLaren","doi":"10.1109/ICECS.2008.4674830","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4674830","url":null,"abstract":"The theft of electronic designs and in particular Intellectual Property (IP) Cores is problematic [1]. Proving a design has been stolen is difficult if not impossible. A method is required to quickly and cheaply identify electronic designs and especially IP Core designs embedded within larger chips or programmed into Field Programmable Gate Arrays (FPGA). This paper introduces a novel thermal tag which will fulfill this requirement.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121253004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Analysis of the critical rise time in MOBILE-based circuits 基于mobile电路的临界上升时间分析
2008 15th IEEE International Conference on Electronics, Circuits and Systems Pub Date : 2008-11-17 DOI: 10.1109/ICECS.2008.4675009
J. Quintana, M. Avedillo
{"title":"Analysis of the critical rise time in MOBILE-based circuits","authors":"J. Quintana, M. Avedillo","doi":"10.1109/ICECS.2008.4675009","DOIUrl":"https://doi.org/10.1109/ICECS.2008.4675009","url":null,"abstract":"It is well known that there is a critical value for the rising time of the clocked bias signal which limits the operating speed of MOBILE-based circuits. This paper analyzes the transient response of a MOBILE-based follower and obtains analytical expressions to calculate the critical value for the rising time of the bias signal below which the circuit does not operate correctly. This analysis has been extended to more complex circuits such as threshold gates, we have also derived operating speed limits for these circuits. Results obtained have been validated through extensive simulations with HSPICE.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133619858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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