{"title":"基于非线性分析的4倍LC注入锁定分频器设计方法","authors":"S. Daneshgar, Michael Peter Kennedy","doi":"10.1109/ICECS.2008.4675059","DOIUrl":null,"url":null,"abstract":"One significant source of power consumption in modern frequency synthesizers at high frequencies is the prescaler block. In order to tackle this problem, analog injection-locked frequency dividers (ILFDs) have been considered rather than conventional digital prescalers. In recent years, diverse and sometimes contradictory algorithms for estimating the locking range in these dividers have been proposed. In this paper, we propose a new method based on nonlinear analysis to design a typical (LC oscillator-based) injection-locked frequency divider and to predict its locking range. In order to support our analysis, we design a divide-by-4 circuit and compare its simulated locking range with theoretical predictions.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"27 18","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis\",\"authors\":\"S. Daneshgar, Michael Peter Kennedy\",\"doi\":\"10.1109/ICECS.2008.4675059\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"One significant source of power consumption in modern frequency synthesizers at high frequencies is the prescaler block. In order to tackle this problem, analog injection-locked frequency dividers (ILFDs) have been considered rather than conventional digital prescalers. In recent years, diverse and sometimes contradictory algorithms for estimating the locking range in these dividers have been proposed. In this paper, we propose a new method based on nonlinear analysis to design a typical (LC oscillator-based) injection-locked frequency divider and to predict its locking range. In order to support our analysis, we design a divide-by-4 circuit and compare its simulated locking range with theoretical predictions.\",\"PeriodicalId\":404629,\"journal\":{\"name\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"volume\":\"27 18\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2008.4675059\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2008.4675059","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis
One significant source of power consumption in modern frequency synthesizers at high frequencies is the prescaler block. In order to tackle this problem, analog injection-locked frequency dividers (ILFDs) have been considered rather than conventional digital prescalers. In recent years, diverse and sometimes contradictory algorithms for estimating the locking range in these dividers have been proposed. In this paper, we propose a new method based on nonlinear analysis to design a typical (LC oscillator-based) injection-locked frequency divider and to predict its locking range. In order to support our analysis, we design a divide-by-4 circuit and compare its simulated locking range with theoretical predictions.