{"title":"超低电压和、非和异或CMOS门","authors":"Y. Berg, O. Mirmotahari, S. Aunet","doi":"10.1109/ICECS.2008.4674986","DOIUrl":null,"url":null,"abstract":"In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"275 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Ultra low voltage and, nor and XOR CMOS gates\",\"authors\":\"Y. Berg, O. Mirmotahari, S. Aunet\",\"doi\":\"10.1109/ICECS.2008.4674986\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.\",\"PeriodicalId\":404629,\"journal\":{\"name\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"volume\":\"275 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2008.4674986\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2008.4674986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we present NAND, NOR and XOR gates exploiting the ultra low-voltage (ULV) CMOS logic style [1] [2]. There are two kinds of NAND and NOR gates available using the ULV logic style; straightforward gates resembling complementary CMOS and threshold holdgates. In addition to NAND and NOR gates we present a minority three gate and an XOR ULV gate. The electrical characteristics of these two approaches are discussed with a focus on delay and noise margins. Simulated data assuming a 90 nm CMOS process is included.
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