{"title":"用于10Gbps SoC传输链路应用的低抖动自校准锁相环","authors":"Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu","doi":"10.1109/ICECS.2008.4674971","DOIUrl":null,"url":null,"abstract":"A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm2.","PeriodicalId":404629,"journal":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","volume":"253 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A low jitter self-calibration PLL for 10Gbps SoC transmission links application\",\"authors\":\"Kuo-Hsing Cheng, Yu-Chang Tsai, Kai-Wei Hong, Yen-Hsueh Wu\",\"doi\":\"10.1109/ICECS.2008.4674971\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm2.\",\"PeriodicalId\":404629,\"journal\":{\"name\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"volume\":\"253 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 15th IEEE International Conference on Electronics, Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2008.4674971\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 15th IEEE International Conference on Electronics, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2008.4674971","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A low jitter self-calibration PLL for 10Gbps SoC transmission links application
A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm2.