Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium最新文献_第7页

Theory And Implementation Of LSSD Scan Ring & STUMPS Channel Test And Diagnosis LSSD扫描环& STUMPS通道检测与诊断的理论与实现

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639890

G. A. Sarrica

{"title":"Theory And Implementation Of LSSD Scan Ring & STUMPS Channel Test And Diagnosis","authors":"G. A. Sarrica","doi":"10.1109/IEMT.1992.639890","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639890","url":null,"abstract":"Today's advanced computer technology renders the use of physically probe-able test pins impractical. Built In Self-Test uses scan rings which provide observability to on-chip latches. This paper discusses the latch-level theory of the scan M y defects that must be tested for and diagnosed, and the implementation of the diagnostic algorithms used. SUMMARY: Modem test methodology eliminates the use of physically probe-able points in the testing of TCM's. This allows for faster testing of the parts and reduces tester complexity. However, this situation creates many challenges in the fields of logic testing, and failure diagnostics if a test reveals a defect. Significant progress has been made using the Built In Self-Test (BIST) concept to accomplish probeless 'TCM test. This concept requires the use of Level Sensitive Scan Design (LSSD) where latches have two methods of propagating data, a scan path and a logic path. The Shift Register Latches (SRLs) are connected in scan chains which provide observability to the results of logic functions performed by the TCM. Before the logic of a chip can be tested, the integrity of its scan path must be verified. This verification is accomplished by applying three scan ring based tests: LSSD Flush, LSSD Scan, and Self-Test Scan. If a scan path proves defective, then diagnostics must be performed to make an effective repair call. This paper deals with the latch level theory of LSSD, the types of defects that can occur in a scan ring, and the tests and software tools that are used to make effective repair calls on faiting parts. Part","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133773225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Molding Of Plastic Components Using Micro-EDM Tools 使用微细电火花加工工具的塑料部件成型

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639879

H. Li, S. Senturia

引用次数: 3

Silicon VLSI Technology Trends 硅VLSI技术趋势

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639915

T. Ning

引用次数: 0

Knowledge Based Decision Support For Surface Mount Infrared Reflow Soldering 基于知识的表面贴装红外回流焊决策支持

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639910

Chien-Hsing Wu, K. Srihari, A. McLenaghan

引用次数: 0

Towards A QML Approach In Electronic Packaging 面向电子封装的QML方法

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639856

A. Dasgupta, S. Verma, R. K. Agarwal

引用次数: 0

High Density Multilayer Substrate For Si On Si High Speed Module 用于Si On Si高速模组的高密度多层基板

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639919

M. Kimura, T. Shimoto, K. Matsui, K. Utsumi, T. Kusaka, T. Koike

{"title":"High Density Multilayer Substrate For Si On Si High Speed Module","authors":"M. Kimura, T. Shimoto, K. Matsui, K. Utsumi, T. Kusaka, T. Koike","doi":"10.1109/IEMT.1992.639919","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639919","url":null,"abstract":"In order to have high speed hardware, there are two approaches. One is to use high speed LSIs. The other is to reduce the mcdia dclay between LSIs. This paper describes the performance by a high density multilayer substrate, based on Si wafer for high speed module. The high density Si multilayer substrate consists of ground layer(Si wafer), power distribution layer(Al), two signal layers(Au), bonding pad(Ni/Au) and four dielectric layers. The signal layer has 20 pm/55 pm line and space. The dielectric layers are made of organic resin having low dielectric constant(e=3.0). Si substrate size is 43mn x 43mm. With high density Si multilayer substrate, thc authors have evaluated various mechanical and electrical characteristics. The adhesion between conduction llayer and organic insulator is excellent. The electric Characteristics (characteristic impedance, crosstalk noise and propagation delay time) are practical too. After mounting LSIs, which are TAB chips, on Si substrate, a high speed RISC chip module packaged 174 pin ceramic PGA has been fabricated. LSI packaging density is 34 % for high efficiency.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126553634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Thermomechanical Characterization Of Flip Chip Solder Bumps For Multichip Module Applications 用于多芯片模块应用的倒装芯片焊料凸点的热力学特性

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1992-09-28 DOI: 10.1109/IEMT.1992.639907

J. Lau

引用次数: 3

Principle And Method Of Dynamic Parameters Measurement For Semiconductor Rectification Devices 半导体整流器件动态参数测量原理与方法

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1900-01-01 DOI: 10.1109/IEMT.1992.639874

Zhao Fu, Ge Shuxin, Ling Zemin, W. Jinghua

引用次数: 0

Failure Analysis Of Power Modules; A Look At The Packaging And Reliability Of Large IGBTs 电源模块的故障分析大型igbt的封装和可靠性

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1900-01-01 DOI: 10.1109/IEMT.1992.639922

H. de lambilly, H. Keser

引用次数: 2

Design Tradeoffs When Using SMT, COB, And/or TAB packaging Technology 使用SMT、COB和/或TAB封装技术时的设计权衡

Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1900-01-01 DOI: 10.1109/IEMT.1992.639917

Elliott H. Newcombe

引用次数: 0