Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium最新文献

{"title":"Generalized Adaptive Image Analyzer","authors":"F.B. Weiskopf, H. Chiu, T. W. Greene, J. A. Becker, F.G. Arcella","doi":"10.1109/IEMT.1992.639887","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639887","url":null,"abstract":"","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125528861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation Of Tab Conductor Materials","authors":"I. Adhihetty, T. Scharr, R. Padmanabhan","doi":"10.1109/IEMT.1992.639858","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639858","url":null,"abstract":"Various types of wrought and electrodeposited copper foils are used in the fabrication of TAB lead frames, The grain structure and mechanical properties of these foils may vary significantly depending on the type and temper of the copper foils. The purpose of this study was to develop and understanding of how the mechanical properties of various copper samples that are currently used in the TAB lead fabrication correlate with the reliability performance (temperature cycle) of selected ILB leads. Tensile modulus, coefficient of thermal expansion (CTE), ultimate tensile strength (UTS), yield strength (YS) and fatigue ductility of all the TAB foils were studied and compared. The results of this study indicated that indeed there was a one-to-one correlation between thermal stress, UTS, fracture strength and fatigue ductility and the reliability performance. Evaluation of thermomechanical properties (including tensile modulus and coefficient of thermal expansion) was achieved through Dynamic Mechanical Thermal Analysis (DMTA). The yield strength, ultimate tensile strength (UTS) and fracture strength were obtained using PL Thermal Sciences MINIMAT , while the fatigue properties were determined through an Instron tester. Failure modes in reliability tested samples were determined through Scanning Electron Microscopy. As a first order approximation, the product of the modulus and CTE ( over the temperature range of interest) may be used to determine the thermal stress during temperature cycling. Materials with minimum thermal stresses are expected to yield improved reliability performance. Similarly, a direct relation also exists between UTS and fracture strength (area under the stress-strain curve) and the reliability performance. Yet another property, the fatigue ductility, may also be used to predict the reliability performance, but strain rate effects have to be considered before arriving at optimal solutions. ExDerirnental Two types of ED (LF-A and LF-B) and three types of wrought ( LF-C, LF-D and LF-E) copper samples were used in the analysis. The modulus and coefficient of thermal expansion (CTE) were obtained using the DMTA-Tensile head. For the evaluation of thermomechanical properties, the specimens were subjected to a known dynamic force. A static force of 1.0-1.2N was applied to provide a positive tension, to prevent specimen buckling due to thermal expansion. The samples were analyzed at two frequencies, viz., 1Hz and 10% over a temperature range of 30\" to 200\" C and at a heating rate of 3\" C/min. Both modulus and CTE values were computed by continuously monitoring the deflection of the samples during the DMTA run. The yield strength and ultimate tensile strength OJTS) were obtained using MINIMAT material tester. Stress-strain curves were generated by increasing the load on the sample at a rate of OSN/min and measuring the deflection of the sample as in DMTA.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131921815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Packaging With Multichip Modules","authors":"H. Charles","doi":"10.1109/IEMT.1992.639892","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639892","url":null,"abstract":"Packaging with multichip modules is rapidly becoming a major thrust in electronic system technology. Multichip modules combine several high-performance silicon or GaAs integrated circuits with a customdesigned multilayer substrate structure which takes full advantage of the integrated circuits' performance (e.g., 100-MHz digital clocks, multi-GHz analog frequencies). These complex \"hybrid\" structures can be fabricated on various substrate materials using several different dielectridmetallization schemes. Because of the high density and high performance of the electronic devices packaged in multichip modules, stringent new demands are being placed on materials, interconnects, and packaging structures. A systematic review of multichip module structures and materials is presented. Module electronic and physical properties are described along with the potential impact of new materials on module performance.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123242883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failure Modes & Effective Analysis And Continuous Improvement","authors":"Mark Hatty, N. Owens","doi":"10.1109/IEMT.1992.639899","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639899","url":null,"abstract":"Failure Modes & Effective Analysis (FMEA) is a design tool which has been used to improve the quality of product and process design, leverage production experience into other areas and achieve continuous improvement for product already in manufacture. FMEA will be briefly described and characterized in order to provide a common frame of reference for discussion. Key practices which support FMEA include the formation of cross- functional teams, empowerment, and project planning. The archival power of FMEA will be closely reviewed as a productivity multiplier. It will show how FMEA can be used to broadly track program improvements and place them in a customer sensitive context. In addition, examples derived from actual semiconductor applications will be presented and discussed in order to gain better insight into the link between FMEA and continuous improvement. Another point of emphasis will be the common difficulties encountered while implementing this engineering tool. A common theme in successful enterprises is the drive for continuous improvement. Whatever is \"best-in-class'' today is being copied by less formidable competitors while one's main rivals are already leaping to the next generation of technology. The successful enterprise is always looking for the new, the better, the quicker, the less costly ways of getting the job done. Today's semiconductor industry is a prima facie example of the \"survival of the fittest\" principle at work. Failure Modes & Effect Analysis (FMEA) is a tool which is gaining recognition in electronics manufacturing. It is an advanced quality planning methodology and a form of structured brainstorming which allows problems to be dissected and broken down into a series of smaller, more manageable bites. Customer communication is a key element of the FMEA process, thus assuring customer requirements define the acceptable level of performance. There are distinctions within FMEA. The Design FMEA examines the design intent of a product or service. The Process FMEA seeks out possible sources of variation in manufacture of the predetermined design. The Design FMEA starts with a \"clean sheet\" of paper and known manufacturing capabilities, so that the end product exactly matches the customer requirements. The Process FMEA looks for things which might go wrong or vary within the manufacturing process and identifies corrective and/or containment actions for each potential condition. As a result of the design and process FMEA, a product has been scrutinized to achieve a more robust design manufactured with a completely characterized process. (1)","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124546475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechatronics Curriculum In The Synthesis Coalition","authors":"D. Auslander, G. Hanidu, A. Jana, S. Landsberger, M. Seif, Y. C. Yong","doi":"10.1109/IEMT.1992.639883","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639883","url":null,"abstract":"Mechatronics curricula are being established at several universities associated with the Synthesis Coalition, a National Science Foundation project. aimed at improving engineering education and increasing the number, quality and diversity of engineering graduates. The programs focus on real time computation and control of mechanical systems such as DC motors, stepping motors, thermal systems, and manufacturing machinery.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Effect Of Sputter Deposition Parameters On Selected Properties Of Titanium-tungsten (TiW) Thin Films","authors":"C. Winter","doi":"10.1109/IEMT.1992.639875","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639875","url":null,"abstract":"Titanium-tungsten (TiW) thin films are used in semiconductor device fabrication as diffusion barriers and fuse structures in programmable logic devices. Patterned fuses require consistent electrical characteristics. This study used a statistically designed experiment (SDE) to investigate and model the effect of TiW sputter deposition parameters on several characteristics of the blanket film and patterned fuses. The SDE input factors are substrate pre-deposition etch time, substrate temperature, deposition pressure, target power, and a post deposition thermal cycle. The responses investigated are biaxial stress, electrical resistivity, reflectivity, thickness uniformity, and the critical current density to blow patterned TiW fuses. Two-factor interactions and quadratic effects are explored. The substrate temperature was found to significantly affect stress, resistivity, and the critical current density. The deposition pressure notably affected stress. The structure zone model concept was employed in explaining the results. SEM, TEM, SIMS, and Auger analyses were also employed to assist in data interpretation. TEM showed that a 400°C deposition produced a more distinct polycrystalline structure with evidence of Ti partitioning observed. TEM diffraction data indicated a b(Ti,W) crystal structure with no evidence of a-Ti. Auger analysis confirmed that the concentrations of oxygen and carbon impurities were minimal and did not significantly affect the variation in the responses monitored. I NTRO DU CTI 0 N Proiect Goal The intent of this study was to characterize the effect of several TiW sputter deposition process parameters on selected properties of the TiW film, and to explain the results from the materials engineering perspective of the structure/property relationship; deposition process conditions influence the film structure obtained, with this structure arfecting the properties and performance of the film. Backaround TiW thin films are used in semiconductor device fabrication as diffusion barriers and fuse structures in programmable logic devices. The addition of 5-10 wt. % titanium provides improved adhesion, barrier, corrosion, and contact resistance properties. The application of sufficient current through a patterned TiW fuse will result in melting, termed \"blowing\", and the loss of electrical continuity. In this manner generic devices can be programmed for custom","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Outer Lead Bonding Process Conditions For TFT-LCD Module","authors":"D. Hu, Shyuan-Jeng Ho, Baotong Tang","doi":"10.1109/IEMT.1992.639904","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639904","url":null,"abstract":"Outer lead bonding (OD) of a TAB tape to a LCD glass panel is an important step in m a h g FT-LCD modules. me OLB process uses a t h e d to heat and press TAB leads against an IT0 patterned glass Hit6 an Anisotropic ConductiE Film (ACF) in k m n . l3e tempenture at the ACF, the ali&ment betwefir TAB leads and IT0 patterns at&.? the integrity of bond betwen the lFT-LCD modules and the TAB IC driver. l&pziment shows that only 20% of the particle contact mea is adequate fir a low interconnection resistance of' -TO Q. The temperature at the interhe between the ACF a!m and the m0 glass is another important parameter. Depc:nding on the thickness of the polyimide h, the temperature ditErence between the thermode and the ACF interhce can be as large as 300 OC. Another parameter used in this study is the \"thennode up\" temperature. Experiments with tw &&rent \"thermode up\" temperaatures of 340 OC and 80 OC wre studied. Mer the OLB bonding, the bonds wnt through temperature cycling betwen -40 OC and 100 'OC fbr 200 cycles. A lower \"thermode up temperature has a sli@tly better resistance to thermal cycling test than those with a Egher \"thennode up\" temperature.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124169439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electronics Manufacturing Research At Rensselaer Polytechnic Institute","authors":"D. Millard, D. Knorr, L. Felton, S. Black","doi":"10.1109/IEMT.1992.639882","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639882","url":null,"abstract":"The 1990's has become the decade of electronics manufacturing. Never before has electronics been as major an element of nearly every product sector. For example, a 1992 automobile contains solid state ignition, computer-controlled fuel injection, automatic anti-skid braking, embedded diagnostics and other electronic components that were never even thought of by 1960's auto manufacturers -making the exponential increase and metamorphosis in electronics manufacturing quite clear. The never-ending desire for greater functionality and higher performance associated with electronics has forced designers to utilize novel, high density packaging technologies to provide theiI products with a competitive edge. Unfortunately, the use of an immature device packaging technology provides those responsible for manufacture of the electronics with an assembly and reliability related nightmare. The predominance of today's devices are being connected to substrates exhibiting .025\" (25mil) pitch density or less. As can be seen in the following figure, this trend will continue to get worse as we approach the year 2000 [l].","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133342560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Conductive Filament Formation In Printed Wiring Boards","authors":"Bi-Chu Wul, M. Pecht, D. Jennings","doi":"10.1109/IEMT.1992.639865","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639865","url":null,"abstract":"In this paper the preliminary results of a study to characterize the conductive filament formation (often called metal migration) of woven fabric printed wiring boards with respect to resin material, board surface coating, applied bias, geometry of the electrodes and spacing between the electrodes are presented.The experiments were accelerated life tests at controlled temperature-humidity-voltage conditions.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128293428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IBM Austin Electronic Card Assembly & Test Manufacturing Quality Management Process","authors":"S. Mulligan, J. Stobaugh","doi":"10.1109/IEMT.1992.639853","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639853","url":null,"abstract":"This paper summarizes Austin Electronic Manufacturing Quality twelve month period Specifically, it describes quality has been Management to Manufz includes the full range Yield Management, process improvement response to customer communications with highlights the busin proposed, the implementation and the results that have the changes made in the IBM Cinrd Assembly & Test (ECAJ) Management Process during the fr-om June 1991 through May 1992. how the responsibility for product transferred from Engineering cturing Management. This transfer of Quality responsibilities including defect investigation, manufacturing actions, defect elimination actions, problems, and continuous ECAT customers. This paper 3ss process strategy that was process that was utilized, been achieved to date.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127065588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}