Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium最新文献

{"title":"A Flexible ASIC CIM System (Orchard II)","authors":"K. Wada, T. Okubo, T. Takeda, C. Hashimoto","doi":"10.1109/IEMT.1992.639870","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639870","url":null,"abstract":"A flexible CIM system for ASIC manufacturing called ORCHARD I1 has been developed, that offers enhanced flexibility of system construction and production line management. It includes modules that handle scheduling, lot tracking, equipment control, data collection and database management. Each module is implemented on distributed workstations to conserve CPU resources. Non-SECS as well as SECS equipment can be easily connected to the system using a ”virtual machine” method. A database schema is automatically generated after designing a data display screen, Collected data are converted into data groups that meet the specific needs of equipment engineers, process engineers, and production line managers based on a ”data processing recipe.” Flexible production line management is achieved using a novel scheduling technology that features a priority evaluation function. With these technologies, even a lowvolume production line can be set up cost-effectively.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"94 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126140897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechatronics Research And Educational Initiatives At Louisiana State University","authors":"L. Keys, T. Liao, R. Hirschfeld","doi":"10.1109/IEMT.1992.639881","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639881","url":null,"abstract":"Louisiana State University's (LSU) Mechaponics Engineering (MTE) initiative is an effort to improve engineering education and research at LSU. MTE brings engineers of various fields together to design and build the next generation of innovative quality products. To accomplish this task, we must better educate all engineers in systems design, group work, and effective communication of ideas. We must also train a new type of engineer who is capable of supervising and coordinating the activity of an MTE team. The LSU approach incorporates: concurrent engineering; computer aided engineering and manufacturing; product life-cycle analysis and design; automation and robotics; mechanical-electrical integrated devices; human interactions with machines; and chip level assembly and design. LSU believes that our MTE education and research initiative will provide both the engineers and the new ideas needed to design highly integrated and intelligent products. In this paper, we present the LSU initiative as an example for other universities and colleges.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125480298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Increasing IC Manufacturing Productivity Using A DVI-based Performance Support System","authors":"L. Baca","doi":"10.1109/IEMT.1992.639901","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639901","url":null,"abstract":"This article describes how ithe Fab 9 DVI@' (Digital Video Interactive) Development Team designed, developed, and implemented Intel's first in-house :application of the DVI technology as a performance support aind information delivery system. After defining interactive multimedia, the article presents a brief overview of the DVI technology, followed by a description of the core personnel involved in the project. Presented next are the purpose and objectives of the pilot application, and the results of a study we conducted indicating that we increased manufacturing productivity. A detailed description follows of the application content, as well as the critical planning and pre-production activities we implemented. Finally, the article discusses user interface design considerations; and recommends specific and critical areas for the future alpplication and study of DVI-based performance support systems and simulators within the integrated circuit (IC) manufacturing industry. The Appendix lists the hardware and software used to develop the application.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116452545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Integrated Expert System Environment For DFM In Surface Mount PCB Assembly","authors":"H. Ugur, K. Srihari","doi":"10.1109/IEMT.1992.639867","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639867","url":null,"abstract":"Surface Mount Technology (SMT) has emerged as the alternative to through hole technology in the Printed Circuit Board (PCB) domain. SMT ,311ows for decreased component sizes, increased performance, and better packing densities. The complexity of SMT coupled with the need to rapidly cope with market changes has necessitated the integration of the design and manufacturing processe 3. The need to remain competitive has resulted in the need to efficiently design a PCB considering manufacturability, testability, reliability, and cost. This research describes an Integrated Expert System Environment (IESE) that helps promote concurrer t engineering of PCB substrates. The IESE and its component sub-systems were developed on a workstation using LISP. The constrL ction of the IESE and its component subsystems is described. Tne inputs and outputs of each sub-system are addressed. Ideas for further research are presented.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124437472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development Of An Appropriate Figure Of Merit To Assess The Effectiveness Of New Product Introduction Into Volume Manufacturing","authors":"D. E. Pope","doi":"10.1109/IEMT.1992.639898","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639898","url":null,"abstract":"","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133174158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Vision Of Manufacturing Quality Management In The Year 2000","authors":"D. Krupka","doi":"10.1109/IEMT.1992.639851","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639851","url":null,"abstract":"we have performed audits, we, too, have found that the majority of our operators do not meet eighth grade standards in English and math. How can we expect teams with such skills to solve reasonably sophisticated problems? The answer is the same as Motorola's training and education. Can manufacturing afford burden? According to MOtorOk Properly managed Programs Pay handsome returns. And there is anecdotal evidence to support this within AT&T. It is these observations that provide the foundation for my second vision of the year 2000. Teams of highly skilled operators organized into highly effective teams. Our challenge for the years ahead is to perform the necessary transformation. e year 2000 includes the","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133695087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Curriculum And Laboratories In Electronics Manufacturing Processes At The University Of Arkansas","authors":"T. L. Landers, E.W. Fant, E.M. Malstrom, W. Brown","doi":"10.1109/IEMT.1992.639885","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639885","url":null,"abstract":"The University of Arkansas Electrical and Industrial Engineering Departments have developed a course in Electronics Manufacturing Processes. The course is part of a program designed for graduate and upper-level undergraduate students from any engineering discipline. It serves as a survey of electronics manufacturing with the objective of promoting concurrent engineering. This paper describes our approach with emphasis on the laboratory component in which interdisciplinary student teams perform CADICAM of printed wiring boards. The students perform design work on Sun workstations and mixed-technology automated assembly in an electronics assembly workcell incorporating robotics and vision technologies. Introduction It is no longer viable for engineers to remain narrowly focused in their individual disciplines. Increasingly, customers demand products of higher quality and lower cost; and there are both technical and competitive pressures to compress product development time. These trends necessitate the concurrent engineering approach, wherein engineers are able to cooperate in interdisciplinary teams to achieve the collective goal of economic success. The product and its manufacturing process must be designed concurrently, and engineers of all disciplines need better understanding of how their activities interact. Design engineers need to know the limitations of the production processes in order to design manufacturable products. Similarly, manufacturing engineers should be knowledgeable about emerging product technologies in order to plan and optimize the manufacturing process. The electronics industry needs engineering graduates who have a good understanding of both design and production, in order to accomplish the objectives of concurrent engineering. College engineering courses have long been available in product/process design and computer-aided design I computer-aided manufacturing (CADICAM) for the metal-working industries; however, no comparable course has been available for the electronics industry. The Departments of Electrical Engineering and Industrial Engineering at the University of Arkansas have addressed this need through initiation of a program in Electronics Manufacturing. The first stage in creation of this program has been development of a course in Electronics Manufacturing Processes. 0-7803-0755-082 $3.00 01992 IEEE 174 The objective of the course is to prepare engineers for entry-level participation in the team environment necessary for successful competition in the world electronics industry. The catalog description states that the course is an introduction to manufacturing processes and concurrent engineering in the electronics industry, providing a survey of electronics components and products and the processes of fabrication and assembly. Principles of design, productivity, quality and economics are presented, with an emphasis on manufacturability. The approach for this course has been consistent with a strategy over the ","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117015113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Module Frequency And Noise Budget Limitations/tradeoffs In Multi-chip Modules As A Function Of CMOS Chips Integration","authors":"R. Senthinathan, J. Prince, A. Cangellaris","doi":"10.1109/IEMT.1992.639918","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639918","url":null,"abstract":"A detailed investigation of the liniitb of module clock frequency, coupled noise, and simultaneous switching noise was performed as a function of CMOS chip integration level of multi-chip assemblies. The objective of this study is to analyze noise limitations, and to predict the system performance as a function of integration level. Results have demonstrated that unwanted coupled noise and siniultaneous switching noise are a major degradation/limitation factor with high levels of integration in multi-chip modules (MCMs). This effect is especially a major limiting factor with scaled and reducedsupply-voltage CMOS chips. Closed-form equations are included to estimate the module frequency and the overall noise budget for MCMs. Design curves are shown for CMOS MCM system frequency, and noise budget limitations are discussed for various levels of chip integrations. Results from case studies on performance and noise limits of future workstation MCMs are explained. I. Introduction and Motivation In order to obtain a high operating clock frequency for a system, not only high-speed integrated circuits (level 1 packaging) are essential, but also higher levels of integration at chip-board (level 2) levels. Multi-chip modules (MCMs) support very high levels of integration. Higher levels of integration in MCMs decrease the average interconnect length between chips, and thereby increase the overall maximum system frequency. Notice that, many performance metrics (electrical, thermal, mechanical, cost, and reliability), and tradeoffs between these metrics are involved in the MCM selection criteria for a system product [1,2]. For a given MCM system design, early estimation of performancecost product merit is essential to determine the market share of this product. In this paper, electrical performance (module clock frequency) and noise budget are analyzed as a function of MCM integration level assuming CMOS chips. Case studies are tailored for future workstation MCM applications, however the equations and methodology are applicable to other MCM applications. With the increase in integration level, the number of signal layers and interconnect density need to be increased for wireability in an MCM. Increase in interconnect density increases crosstalk. In addition, increase in integration level increases the total power dissipation. Reduction in CMOS supply voltage (VD~) reduces chip junction temperature and total power dissipation. However, reduced supply voltage increases noise to signal ratio. To have a reliable MCM system design, it is important to keep the noise to signal ratio to within the maximum allowable limit. Maximum tolerable noise level (noise immunity) depends on both noise pulse amplitude and width. For example, CMOS input receiver noise immunity is shown in Figure 1.0 as il function of channel length [3]. Increase in data/address bus width and operating frequency increases simultaneous switching noise (SSN). Detailed analysis on CMOS simultaneous sw","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123992919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis Of Cluster Tool Performance In Semiconductor Manufacturing","authors":"J. Mauer, Roland E. A. Schelasin, P. Miller","doi":"10.1109/IEMT.1992.639876","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639876","url":null,"abstract":"","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130521385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Design Database For Stripline Interconnections","authors":"J. H. Hohl, O. Palusinski, K. F. Menezes, H. Patel, S.M. Smith","doi":"10.1109/IEMT.1992.639868","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639868","url":null,"abstract":"The advancing semiconductor technologies are unabatedly raising the circuit and device performance. This, in turn, raises the demands on the signal propagation characteristics of the chip and module interconnecting systems. As these requirements become ever tighter, better design aids become indispensable. The experience with an experimental design database to form the core of a stripline CAD program is described. The design space can be covered with a sufficiently small number of points to allow instantaneous response from the necessary scanning and interpolation operations, while accuracies better thm 1 % can be achieved. A database allows the determination of electrical parameters from line cross-section geometries as well as the inverse, i.e., the establishment of line geometries for given electrical parameters, with comparable ease. The scaling properties of transmission line systems permit very efficient coverage of the design space at the cost of added intricacies in the database organization and in the scanning algorithms. A contemporary personal computer is fully adequate to run the resulting CAD program. However, more powerful machines are preferable for the one-time numerical computations for generating the database. A CAD program with swift response is an effective solution to these problems. Such a program can be developed around a database consisting of pre-computed electrical parameters for line geometries that uniformly cover the design space, i.e., the ranges of the geometrical dimensions reasonably achievable by a technology. In such an approach, the intricacies associated with numerical solutions of the boundary value problems are only faced once, during generation of the database, and can be relegated to the experts. Once the database is established, electrical parameters for given line geometries, or line geometries for given electrical parameters, can be determined by table-lookup and interpolatlon routines. These routines are fast enough to provide literally instantaneous response, making such CAD programs truly interactive. In the next section, the theory of multi-conductor transmission lines is briefly reviewed and the equations for calculating the electrical parameters of a two-conductor system are given. To illustrate the concept of a database-driven CAD program, a specific database for the two-line system is used here as an example. The inductances and capacitances were computed with the parameter extraction program UAC, developed at the University of Arizona, [I], [a] The main design considerations for the database are discussed in Section 3.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126636650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}