Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium最新文献

{"title":"Divide And Merge Image Processing For Pattern Defect Analysis Of Printed Circuit Boards","authors":"M. Ito, Y. Nikaido, M. Hoshino","doi":"10.1109/IEMT.1992.639886","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639886","url":null,"abstract":"This paper presents a methodology for an optical inspection of a large printed circuit board with fine pithes. Since there exist some limitations due to the available line sensors, memory capacity, and the processors, a sequential scan is suggested to collect a number of subimages (partially divided images) of the entire board. All pattern information obtained from each subimage should be integrated to yield total information about the board. The divide and merge image processings are discussed. Recent addition of a new preprocessing to the initial system reduces imaginary or fault defect appearance rate, which in turn makes it easy to analyze multiple defects effectively. The results of the current system is are demonstrated and some inspected examples are also presented.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123877827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Defense Manufacturing Environment, Change Is The Only Constant","authors":"G. Fugate, P. Thomas","doi":"10.1109/IEMT.1992.639912","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639912","url":null,"abstract":"The defense industry has received much attention in the past year as the result of downsizing operations brought on by the shrinking defense budget. Change, while recently brought to the public's eye, is not a new concept to the electronic equipment manufacturing segment at Texas Instruments. The last fifteen years has brought on major changes in both the structure and operating philosophy of this business segment. Operating division boundaries have changed repeatedly in an effort to keep a logical, technologically sound structure in place to support ever changing business demands. Manufacturing facilities have transitioned at a slower pace but in far more radical ways. In the late seventies and early eighties facilities were built around specific product lines and in some cases specific products. Multiple program single product shops did not exist except in the largest of facilities and then only to support front end operations such as metal fabrication and pre-PWB assembly operations. Assembly and test operations were performed in dedicated areas that were constructed to support a specific product at a predetermined build rate. The dynamic environment of the nineties is precipitating major changes in this approach. Product volumes are dropping while development to manufacturing cycle time requirements are being compressed. Even if time existed to build dedicated facilities, increased competition in a shrinking marketplace has resulted in profitability demands that cannot support large capital investments. The clear direction in this environment is to create flexible factories that can support multiple product lines in both a development and production environment.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"350 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125630056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Role And Measurement Of Trimming Shock On Component Lead","authors":"David Wolfovitz, D. Barker, M. Pecht","doi":"10.1109/IEMT.1992.639863","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639863","url":null,"abstract":"Lead trimming is a standard operation performed during printed circuit board assembly. The trimming activity is generally conducted on discrete components before attachment to the board, or after solder attachment of through hole mounted components. The purpose of the trimming operation is to cut any excess lead to a specified length. This paper describes the detrimental effects of trimming shock on some component types and presents a method for qualitative measurement of trimming shock. During the trimming operation the cutter wedges itself into the lead resulting in a local tensile stress in the lead material between the two cutter faces. The magnitude of this tensile stress is a function of the cutter geometry. The shock wave, or more properly the stress wave, that is generated in the cutting action is related to the catastrophic crack propagation or tensile failure 'of the lead upon completion of the cut. Tensile failure or fracture instability occurs, when upon the creation of new surface area or crack extension, the elastic energy released remains larger then the crack resistance. This surplus of released energy can be converted into kinetic energy and is associated with the rapid movement of the material at each side of the crack or cut. During lead trimming the lead is split into two entities, one which remains attached to the component, and another which is removed. The energy released during the catastrophic tensile failure or crack propagation ahead of the cutting edge induces a stress wave in the trimmed lead which is still attached to the component. Similarly the trapped stress wave in the free end of the lead results in it flying across the room. Failures can be induced in the component due to the stress wave created in the trimming operation. Table-1 lists the potential failure sites and associated the failure mechanisms. This paper presents a means to qualitatively measure the stress wave generated in the trimming operation and presents the results for three different type of commonly used cutters. Trimming shock is a commonly overlooked failure mechanism. Production yield can be improved by considering some of the methods suggested in the paper to reduce the shock magnitude. Two different failure sites are considered for the stresses induced by the trimming shock; the lead seal and the wire bond area at the lead termination within the package.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114829813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Printed Circuit Board Assembly/soldering Initiatives At Penn State","authors":"E.A. Lehtihet","doi":"10.1109/IEMT.1992.639884","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639884","url":null,"abstract":"Surface mount technology ( SMT ) is having a significant impact in the printed circuit board industry given implications of this technology on component sizelweight considerations, board density, assembly and testing. Large segments of the industry are converting from through hole technology to surface mount and engineers find they have to master new processes and keep informed of new developments. With initial support from the AT&T Manufacturing Foundation and current support from the National Science Foundation, the Industrial Engineering Department at Penn State has developed a laboratory to support most processes required for assembly of printed circuit boards with mixed technology. This paper provides a brief description of two recent educational initiatives involving this technology as well as other aspects of electronic manufacturing.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117337181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electronic Manufacturing At The University Of Kentucky","authors":"R. S. Heard","doi":"10.1109/IEMT.1992.639880","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639880","url":null,"abstract":"In both the size of funding and in the focus on interdisciplinary approaches to problem solving, the Center is comparable to the several Engineering Research Centers recently established with NSF funding. However, it is unique among university engineering research centers in that it contains an industrial extension program within the same organization. It is also among only a handful of universities offering graduate degrees in Manufacturing Systems Engineering.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114948109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"\"Generating Three Dimensional Models Of Solder Joints Using X-ray Laminography\"","authors":"S. Black","doi":"10.1109/IEMT.1992.639889","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639889","url":null,"abstract":"","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126164235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Encapsulation Of Flip Chip Structures","authors":"S. Machuga, S. Lindsey, K. Moore, A. Skipor","doi":"10.1109/IEMT.1992.639861","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639861","url":null,"abstract":"Flip chip technology, applied to printed wire board substrates, offers a minimization of IC package size on conventional, low cost assemblies as well as a reduction in interconnect inductance. Extensive mechanical fatigue of flip chip interconnects during thermal cycling is of critical concern due to the severe thermal expansion rate mismatch between the silicon die and typical organic substrates. In this study, an extensive thermomechanical finite element analysis of flip chip assemblies suggests that the thermal cycle reliability of the interconnections can be dramatically enhanced through the introduction of a rigid encapsulant layer between the chip and the substrate. Through an understanding of the mechanics of the assembly, the effects of geometrical design and material properties on interconnect thermal cycle performance and induced stress on the silicon device were predicted. Based on thew results, a flip chip structure employing a conventional FR4 substrate was constructed and was found to have exceptional thermal cycle reliability. An analysis of material requirements and proces!;ing constraints is also presented.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Identifying The Source Of Dust Produced During LSI Fabrication","authors":"H. Takeuchi","doi":"10.1109/IEMT.1992.639873","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639873","url":null,"abstract":"A quick and convenient system for identifying accidental dust sources has been developed for LSI cleanrooms. The identification system is based on two kinds of characterization methods of the cleanroom dust generation rate monitor data. One is the characterization of the shape of the curve showing the relationship between the dust generation rate and time using the Weibull parameters, and the other is characterization by dust particle size distribution. Dust generated by moving workers and dust due to accidental leakage of water mist from a bench used to rinse wafers can be readily distinguished and identified by the system.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Fine Pitch And High Aspect Ratio Bump Array For Flip-chip Interconnection","authors":"H. Yamada, Y. Konooh, M. Saito","doi":"10.1109/IEMT.1992.639906","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639906","url":null,"abstract":"This paper describes a bump-fabrication process for a fine pitch and high aspect ratio bump array. The fabricated bumps had a 10 pm pitch with a 5 Dm diameter and a 20 D m height, and were arranged 5 pm apart from each other. The bumps were made of a copper base pillar and a solder cap, and were located on the device circuit area to realize high reliability flip-chip interconnections. A microstructual resist patterning technique to form a fine pitch and high aspect ratio bump array has been developed. The characteristics of the positive type photoresist were investigated to explicate the fundamental behaviors by evaluating the alkaline solubility and the dissolution effect. Also, the factors which affect the resist patterning accuracy were also elucidated to obtain precise resist pattern.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116483159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Automated 3D X-ray Inspection Of Fine Pitch PCB's","authors":"R. Hanke, T. Weiss, N. Petsch","doi":"10.1109/IEMT.1992.639888","DOIUrl":"https://doi.org/10.1109/IEMT.1992.639888","url":null,"abstract":"The visuell inspection of printed circuit boards (PCB's) by human controllers is still an often applied method. However, increasing complexity of electronic fine pitch devices and application of spatial modules makes this way of testing more and more problematic and some defect characteristics can't be judged only by visual inspection systems. A typical example is the testing of SMD solder joints, which can be checked properly only by x-ray methods. In this paper the recently developed x-ray system 3D-DELTA (3-dim. Defect Localization and depht Analysis) for automatic PCB testing is presented. The system was developed for faster spatial data extraction by use of only two x-ray images of the PCB's. The result is the 3-dimensional classification of defects within solder joints and of the solder joints itself without the use of complex computer tomographic algorithms. First the x-ray imaging system for data acquisition is shown. In order to achieve the required data for evaluation, two micro focus x-ray sources are used to produce a stereo image pair during one scan. The use of a line scanning x-ray detector allows the image acquisition line by line with contrast enhancement during object movement. Time loss by stop and go of the assembly line is avoided with this method. Second the data preparation by matching and subsequent division of an adapted reference image from the x-ray data is described. Finally the algorithm for testing the solder joints for completeness and faint flaws is outlined. A combination between absolute thickness measurement by evaluation of polychromatic intensity distribution of the solder pads and 3D-localization by stereoscopic technics is presented.","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126746681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}