Module Frequency And Noise Budget Limitations/tradeoffs In Multi-chip Modules As A Function Of CMOS Chips Integration

Abstract

A detailed investigation of the liniitb of module clock frequency, coupled noise, and simultaneous switching noise was performed as a function of CMOS chip integration level of multi-chip assemblies. The objective of this study is to analyze noise limitations, and to predict the system performance as a function of integration level. Results have demonstrated that unwanted coupled noise and siniultaneous switching noise are a major degradation/limitation factor with high levels of integration in multi-chip modules (MCMs). This effect is especially a major limiting factor with scaled and reducedsupply-voltage CMOS chips. Closed-form equations are included to estimate the module frequency and the overall noise budget for MCMs. Design curves are shown for CMOS MCM system frequency, and noise budget limitations are discussed for various levels of chip integrations. Results from case studies on performance and noise limits of future workstation MCMs are explained. I. Introduction and Motivation In order to obtain a high operating clock frequency for a system, not only high-speed integrated circuits (level 1 packaging) are essential, but also higher levels of integration at chip-board (level 2) levels. Multi-chip modules (MCMs) support very high levels of integration. Higher levels of integration in MCMs decrease the average interconnect length between chips, and thereby increase the overall maximum system frequency. Notice that, many performance metrics (electrical, thermal, mechanical, cost, and reliability), and tradeoffs between these metrics are involved in the MCM selection criteria for a system product [1,2]. For a given MCM system design, early estimation of performancecost product merit is essential to determine the market share of this product. In this paper, electrical performance (module clock frequency) and noise budget are analyzed as a function of MCM integration level assuming CMOS chips. Case studies are tailored for future workstation MCM applications, however the equations and methodology are applicable to other MCM applications. With the increase in integration level, the number of signal layers and interconnect density need to be increased for wireability in an MCM. Increase in interconnect density increases crosstalk. In addition, increase in integration level increases the total power dissipation. Reduction in CMOS supply voltage (VD~) reduces chip junction temperature and total power dissipation. However, reduced supply voltage increases noise to signal ratio. To have a reliable MCM system design, it is important to keep the noise to signal ratio to within the maximum allowable limit. Maximum tolerable noise level (noise immunity) depends on both noise pulse amplitude and width. For example, CMOS input receiver noise immunity is shown in Figure 1.0 as il function of channel length [3]. Increase in data/address bus width and operating frequency increases simultaneous switching noise (SSN). Detailed analysis on CMOS simultaneous switching noise including negative feedback effects is given in [4]. Behavior of CMOS output switching noise with device scaling are explained in [5]. To minimize delay contribution from output drivers, their current drive capabilities are increased. Increase in current drive incrmses the switching current, and thereby switching noise increases. In this paper, simultaneous switching ground noise is analyzed. Power noise calculations are similar due to symmetry between VDD and VSS chip-package connections. One problem with switching noise is modeling an effective LVSS as seen by output drivers with their chip-parkage Vss connections. A method of calculating “Lvss” for a single chip is given in [6]. In this work, a method of modeling “Lvss” for MCMs is attempted. Simultaneous switching noise for future CMOS MCMs is calculated and limitations are explained.