{"title":"面向电子封装的QML方法","authors":"A. Dasgupta, S. Verma, R. K. Agarwal","doi":"10.1109/IEMT.1992.639856","DOIUrl":null,"url":null,"abstract":"~This paper discusses validation, process verif in an integrated QML The distinctions between verification functions approach is presented analysis, simulation and product validation is to hierarchize the manufacturing variables life-cycle cost. Case applications of the mair. 1","PeriodicalId":403090,"journal":{"name":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Towards A QML Approach In Electronic Packaging\",\"authors\":\"A. Dasgupta, S. Verma, R. K. Agarwal\",\"doi\":\"10.1109/IEMT.1992.639856\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"~This paper discusses validation, process verif in an integrated QML The distinctions between verification functions approach is presented analysis, simulation and product validation is to hierarchize the manufacturing variables life-cycle cost. Case applications of the mair. 1\",\"PeriodicalId\":403090,\"journal\":{\"name\":\"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-09-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1992.639856\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Thirteenth IEEE/CHMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1992.639856","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
~This paper discusses validation, process verif in an integrated QML The distinctions between verification functions approach is presented analysis, simulation and product validation is to hierarchize the manufacturing variables life-cycle cost. Case applications of the mair. 1