Theory And Implementation Of LSSD Scan Ring & STUMPS Channel Test And Diagnosis

Abstract

Today's advanced computer technology renders the use of physically probe-able test pins impractical. Built In Self-Test uses scan rings which provide observability to on-chip latches. This paper discusses the latch-level theory of the scan M y defects that must be tested for and diagnosed, and the implementation of the diagnostic algorithms used. SUMMARY: Modem test methodology eliminates the use of physically probe-able points in the testing of TCM's. This allows for faster testing of the parts and reduces tester complexity. However, this situation creates many challenges in the fields of logic testing, and failure diagnostics if a test reveals a defect. Significant progress has been made using the Built In Self-Test (BIST) concept to accomplish probeless 'TCM test. This concept requires the use of Level Sensitive Scan Design (LSSD) where latches have two methods of propagating data, a scan path and a logic path. The Shift Register Latches (SRLs) are connected in scan chains which provide observability to the results of logic functions performed by the TCM. Before the logic of a chip can be tested, the integrity of its scan path must be verified. This verification is accomplished by applying three scan ring based tests: LSSD Flush, LSSD Scan, and Self-Test Scan. If a scan path proves defective, then diagnostics must be performed to make an effective repair call. This paper deals with the latch level theory of LSSD, the types of defects that can occur in a scan ring, and the tests and software tools that are used to make effective repair calls on faiting parts. Part