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A Ka-band asymmetrical stacked-FET MMIC Doherty power amplifier 一种ka波段非对称堆叠fet MMIC Doherty功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969102
Duy P. Nguyen, T. Pham, A. Pham
{"title":"A Ka-band asymmetrical stacked-FET MMIC Doherty power amplifier","authors":"Duy P. Nguyen, T. Pham, A. Pham","doi":"10.1109/RFIC.2017.7969102","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969102","url":null,"abstract":"We present a stacked-FET monolithic millimeter-wave (mmW) integrated circuit Doherty power amplifier (DPA). The DPA employs a novel asymmetrical stack gate bias to achieve high power and high efficiency at 6-dB power back-off (PBO). The circuit is fabricated in a 0.15-µm enhancement mode (E-mode) Gallium Arsenide (GaAs) process. Experimental results demonstrate output power at 1-dB gain compression (P1dB) of 28.2 dBm, peak power added efficiency (PAE) of 37% and PAE at 6-dB PBO of 27% at 28 GHz. Measured small signal gain is 15 dB while the 3-dB bandwidth covers from 25.5 to 29.5 GHz. Using digital predistortion (DPD) with a 20 MHz 64 QAM modulated signal, an adjacent channel power ratio (ACPR) of −46 dBc has been observed.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125718432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Accurate modelling and optimization of inhomogeneous substrate related losses in SPDT switch IC design for WLAN applications 无线局域网应用SPDT开关IC设计中与非均匀基板相关损耗的精确建模和优化
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969034
Fadoua Gacim, P. Descamps
{"title":"Accurate modelling and optimization of inhomogeneous substrate related losses in SPDT switch IC design for WLAN applications","authors":"Fadoua Gacim, P. Descamps","doi":"10.1109/RFIC.2017.7969034","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969034","url":null,"abstract":"This paper teaches the way to achieve an optimum substrate isolation in RF switch design thanks to Deep Trenches Isolation (DTI). The role of Deep Trench Isolation in substrate coupling around active blocks is analysed in link to its ability to break the conductive buried layers in the substrate. Then, an accurate modelling approach based on quasi-static approach developed for inhomogeneous substrate is investigated. The efficiency of this methodology is first demonstrated thanks to a comparison with a standard numerical method based on FEM (Finite Element Method). Then, experiments data are provided to support this theoretical analysis. The methodology is fully integrated in a commercial design flow and offers a perfect trade-off between accuracy and run time simulation. From available test data on single device and a full SP3T, a correlation better than 0.1dB is obtained between simulation and measurement up to 8 GHz.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130282942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RF NMOS switch with dedicated sinks for reduced leakage current RF NMOS开关，专用水槽，减少泄漏电流
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969022
M. Al-Sa'di, J. Donkers, P. Magnée, I. Brunets, J. Slotboom
{"title":"RF NMOS switch with dedicated sinks for reduced leakage current","authors":"M. Al-Sa'di, J. Donkers, P. Magnée, I. Brunets, J. Slotboom","doi":"10.1109/RFIC.2017.7969022","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969022","url":null,"abstract":"In this paper we introduce a method to significantly reduce the substrate leakage current in an RF NMOS switch device without degrading the device figure-of-merit (Ron×Coff), and with no increase in device complexity. This is based on modifying the structure layout, and introducing dedicated sinks. These sinks prevent the substrate's minority carriers from reaching the source/drain regions, thereby removing it from the signal path. In addition, this approach allows independent tuning of two parameters, leakage and Ron×Coff figure-of-merit.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129209793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CMOS integrated galvanically isolated RF chip-to-chip communication utilizing lateral resonant coupling 利用横向谐振耦合的CMOS集成电隔离射频片对片通信
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969065
M. Javid, R. Burton, K. Ptáček, J. Kitchen
{"title":"CMOS integrated galvanically isolated RF chip-to-chip communication utilizing lateral resonant coupling","authors":"M. Javid, R. Burton, K. Ptáček, J. Kitchen","doi":"10.1109/RFIC.2017.7969065","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969065","url":null,"abstract":"In this work, a high voltage (HV) galvanically isolated chip-to-chip communication circuit utilizing laterally coupled resonators is reported. The adjacently placed resonators provide high voltage galvanic isolation (GI) using horizontal space between resonators filled with oxide, which minimizes the need for thick inter-metal dielectrics. A previously unexplored application for lateral coupling is introduced as a passive communication channel for GIs. Magnetic coupling between resonators is used to transfer an upconverted digitally-modulated OOK control signal at 2.8 GHz through the galvanic isolator. This proposed method can be integrated using CMOS processes, without altering the native process or adding extra fabrication steps. The system is realized in a 0.25 µm BCD (Bipolar-CMOS-DMOS) process with only four metal layers for proof of concept. The design does not require exotic packaging and provides 3.3kV RMS isolation, small physical area of 0.95mm2, and sub-20ns propagation delay. The implemented resonators inherently act as bandpass filters, thus enhancing circuit noise immunity to common mode transients.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125277005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 71–86 GHz bidirectional image selection transceiver architecture 一种71-86 GHz双向选图收发器结构
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969098
Najme Ebrahimi, J. Buckwalter
{"title":"A 71–86 GHz bidirectional image selection transceiver architecture","authors":"Najme Ebrahimi, J. Buckwalter","doi":"10.1109/RFIC.2017.7969098","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969098","url":null,"abstract":"A bidirectional image selection transceiver is presented that operates over 71–76 GHz and 81–86 GHz with only 3 GHz of LO tuning range. A sliding-IF architecture with bidirectional VGAs allows operation in transmit and receive modes. The sliding IF and narrow LO tuning range allow wideband image rejection using a single stage polyphase filter. The circuit is implemented in a 90-nm SiGe BiCMOS process. Measurements indicate conversion gain of −2.5 dB to 3 dB with less than ±0.75 dB variation over 10 GHz in TX mode and −4dB to 0 dB with less than ±1 dB variation over 10 GHz bandwidth in RX mode. With 16- and 64-QAM, the EVM is below 5% and 4% at data rates of 6 Gb/s and 9 Gb/s. The RF and LO circuitry consumes at most 150 mW and 250 mW.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129078473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
85–110 GHz CMOS tunable nonreciprocal transmission line with 45 dB isolation for wideband transceivers 85-110 GHz CMOS可调谐非互易传输线，45 dB隔离，用于宽带收发器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969073
C. Yang, P. Gui
{"title":"85–110 GHz CMOS tunable nonreciprocal transmission line with 45 dB isolation for wideband transceivers","authors":"C. Yang, P. Gui","doi":"10.1109/RFIC.2017.7969073","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969073","url":null,"abstract":"The first CMOS nonreciprocal transmission line (TL) for wideband tunable full-duplex transceiver front ends, having over 45 dB isolation in a bandwidth of 1.5 GHz and tuning range of 85–110 GHz, is demonstrated. Offering tunable nonreciprocal propagation, this structure is based on a parametric time-varying TL modulated by a 10 GHz signal through distributed capacitive mixing. Two capacitive mixers together with a biasing network form a resonant type of wideband matching. Implemented in a chip area of 0.245 mm2 in 65 nm CMOS, this nonreciprocal TL achieves over 45 dB isolation throughout its entire bandwidth, a maximum 6.5 dB insertion loss (IL) and over 10 dB return loss.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133762231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Energy efficient distributed-oscillators at 134 and 202GHz with phase-noise optimization through body-bias control in 28nm CMOS FDSOI technology 采用28nm CMOS FDSOI技术，通过体偏置控制实现相位噪声优化的134 ghz和202GHz高能效分布式振荡器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969041
R. Guillaume, F. Rivet, A. Cathelin, Y. Deval
{"title":"Energy efficient distributed-oscillators at 134 and 202GHz with phase-noise optimization through body-bias control in 28nm CMOS FDSOI technology","authors":"R. Guillaume, F. Rivet, A. Cathelin, Y. Deval","doi":"10.1109/RFIC.2017.7969041","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969041","url":null,"abstract":"Two compact frequency generation topologies based on distributed oscillator architecture have been for the very first time integrated at 134GHz and 202GHz in a 10ML 28nm FDSOI CMOS technology. The efficient fundamental frequency generation enables output powers of 0.4dBm and 0.3dBm and 5.5% and 5.4% DC-to-RF efficiency respectively. The body tie of the 28nm FDSOI technology allows phase noise fine tuning through body-bias control. The measured optimum phase noises are −99.6dBc/Hz and −100.4dBc/Hz at 1MHz offset, for the two different oscillators. Robust design has been as well demonstrated, opening the way to mmW and sub-mmW SoC integration in deep submicron FDSOI CMOS.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134413205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
95µW 802.11g/n compliant fully-integrated wake-up receiver with −72dBm sensitivity in 14nm FinFET CMOS 95µW 802.11g/n兼容全集成唤醒接收器，灵敏度为- 72dBm，采用14nm FinFET CMOS
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969045
E. Alpman, Ahmad Khairi, Minyoung Park, V. Somayazulu, J. Foerster, A. Ravi, S. Pellerano
{"title":"95µW 802.11g/n compliant fully-integrated wake-up receiver with −72dBm sensitivity in 14nm FinFET CMOS","authors":"E. Alpman, Ahmad Khairi, Minyoung Park, V. Somayazulu, J. Foerster, A. Ravi, S. Pellerano","doi":"10.1109/RFIC.2017.7969045","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969045","url":null,"abstract":"A 2.4GHz fully-integrated Wi-Fi compliant wake-up receiver in 14nm FinFET technology is presented. The receiver achieves −72dBm sensitivity and +20dBr adjacent channel interference rejection for 62.5kbps at 10−3 BER while consuming 95µW. The OOK-modulated wake-up packet can be transmitted using any legacy OFDM Wi-Fi transmitter.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133201294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 12-b, 1-GS/s 6.1 mW current-steering DAC in 14 nm FinFET with 80 dB SFDR for 2G/3G/4G cellular application 12-b, 1-GS/s 6.1 mW电流转向DAC, 14nm FinFET, 80db SFDR，适用于2G/3G/4G蜂窝应用
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969064
Jaekwon Kim, W. Jang, Yanghun Lee, Seunghyun Oh, Jongwoo Lee, T. Cho
{"title":"A 12-b, 1-GS/s 6.1 mW current-steering DAC in 14 nm FinFET with 80 dB SFDR for 2G/3G/4G cellular application","authors":"Jaekwon Kim, W. Jang, Yanghun Lee, Seunghyun Oh, Jongwoo Lee, T. Cho","doi":"10.1109/RFIC.2017.7969064","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969064","url":null,"abstract":"A 14nm FinFET CMOS 12-b current-steering digital-to-analog (DAC) for 2G/3G/4G cellular applications is presented. A bit segmentation of 6-bit thermometer and 6-bit binary is adopted, and it utilizes the dynamic element matching (DEM) technique to suppress the spurious tones caused by the current source mismatches in 3-D FinFETs. In addition, to keep the voltage drop across each transistor within long-term reliability limit, output switches are designed with shielding transistors while achieving make-before-break operation with the proposed low crossing point level shifter. The active area of a single DAC is 0.036 mm2, and its power consumption is 6.1 mW with SFDR of 80 dBc.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128973551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Sub-THz source integrated in low-cost Silicon Photonic technology targeting 40 Gb/s wireless links 亚太赫兹源集成在低成本硅光子技术目标40 Gb/s无线链路
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969021
E. Lacombe, F. Gianesello, C. Durand, G. Ducournau, C. Luxey, D. Gloria
{"title":"Sub-THz source integrated in low-cost Silicon Photonic technology targeting 40 Gb/s wireless links","authors":"E. Lacombe, F. Gianesello, C. Durand, G. Ducournau, C. Luxey, D. Gloria","doi":"10.1109/RFIC.2017.7969021","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969021","url":null,"abstract":"Following the race for transmitting/receiving at higher data rate, we can observe intensive development of millimeter-wave wireless systems in low-cost CMOS technology. Data rates above 10 Gb/s are now targeted in order to address the data traffic bottleneck of backhaul links for the 5G wireless network. To do so, antenna-systems operating at sub-THz frequencies show great potential, leveraging high-performance photonic technology. This paper presents a sub-THz source based on a SiGe PIN photodiode integrated in low-cost Silicon Photonic technology. Using a laser beat-note, the photodiode delivers an output power ranging from −20 dBm to −29 dBm between 125 and 325 GHz. Leveraging this wide operating band, data rate exceeding 40 Gb/s can be targeted.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116086756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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