{"title":"An S/X-band CMOS power amplifier using a transformer-based reconfigurable output matching network","authors":"Jaeyong Ko, Sungho Lee, S. Nam","doi":"10.1109/RFIC.2017.7969088","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969088","url":null,"abstract":"A dual-band power amplifier (PA) with an integrated reconfigurable transformer is presented. The PA operating in the S/X-band is fully integrated using a 0.18-µm RF CMOS process. The switchable transformer is designed by tuning its primary winding and a shunt capacitor at 50Ω load with passive efficiency more than 62%/67% for S/X-band. The measurement results show saturated output power (PSAT) of 24.3/21.2 dBm with peak drain efficiency (DE) of 34.8%/12.2% at 3.1/8.0 GHz, respectively. The 1-dB bandwidth is 0.7/1.25 GHz (2.8–3.5/7.5–8.75 GHz) for the S/X-band. This amplifier with the proposed transformer is suitable for use in an integrated dual-band high-resolution radar transceiver.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116645320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fully integrated 75–83 GHz FMCW synthesizer for automotive radar applications with −97 dBc/Hz phase noise at 1 MHz offset and 100 GHz/mSec maximal chirp rate","authors":"J. Vovnoboy, Run Levinger, N. Mazor, D. Elad","doi":"10.1109/RFIC.2017.7969026","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969026","url":null,"abstract":"We present a SiGe BiCMOS fully integrated 75–83 GHz FMCW synthesizer for automotive radar applications. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism was incorporated in a dual path PLL, providing low loop bandwidth variation over the whole output frequency range, −97 dBc/Hz phase noise at 1 MHz offset and maximum chirp rate of 100 GHz/mSec.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jang-hoon Han, Jinhyun Kim, Jeongsoo Park, Jeong-Deok Kim
{"title":"A Ka-band 4-ch bi-directional CMOS T/R chipset for 5G beamforming system","authors":"Jang-hoon Han, Jinhyun Kim, Jeongsoo Park, Jeong-Deok Kim","doi":"10.1109/RFIC.2017.7969012","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969012","url":null,"abstract":"This paper presents a Ka-band 4-channel bi-directional T/R chipset in 65 nm CMOS technology for 5G beamforming system. The proposed T/R chipset can provide bi-directional operation with moderate gain and dual polarization. Each channel consists of bi-directional gain blocks, a 5-bit step attenuator and a 5-bit phase shifter including tuning bits. The phase and attenuation coverage are 348° with the LSB of 11.25° and 31 dB with the LSB of 1 dB, respectively. The gain of 13 dB (Tx mode) and 6 dB (Rx mode) are achieved at 28 GHz including the 4-way power divider/combiner.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123465983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fully-scalable 2D THz radiating array: A 42-element source in 130-nm SiGe with 80-µW total radiated power at 1.01 THz","authors":"Zhi Hu, R. Han","doi":"10.1109/RFIC.2017.7969095","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969095","url":null,"abstract":"This paper presents a 1-THz radiating array using IHP 130-nm SiGe process. It is based on a highly-scalable 2D structure that uses a square grid of slots to simultaneously (1) maximize and synchronize the fundamental oscillation (ƒ<inf>0</inf>=250 GHz) and 4<sup>th</sup>-harmonic generation (4ƒ<inf>0</inf>=1 THz) of a large array of transistors, (2) synthesize standing-wave patterns with near-field cancellation at ƒ<inf>0</inf>, 2ƒ<inf>0</inf> and 3ƒ<inf>0</inf> and efficient radiation at 4ƒ<inf>0</inf>. The compact design enables implementation of 42 coherent radiators on a 1-mm<sup>2</sup> area. The chip consumes 1.1-W DC power and generates 80-µW total radiated power with 13-dBm EIRP.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121700678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A split-array, C-2C switched-capacitor power amplifier in 65nm CMOS","authors":"Zhidong Bai, Wen Yuan, A. Azam, J. Walling","doi":"10.1109/RFIC.2017.7969086","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969086","url":null,"abstract":"A multiphase RF, C-2C split-array switched-capacitor power amplifier (SCPA) is introduced that allows the resolution and quality factor of the SCPA to be independently controlled. This allows the SCPA to be designed up to the resolution limit of the process, as determined by capacitor matching and jitter in the clock. In prior SCPAs, the resolution was limited by the choice of the output matching network quality factor and the minimum sized capacitor available in the process. A split-array, C-2C SCPA is implemented in 65nm CMOS and occupies 0.85×2mm2. It delivers a peak output power of 24.05 dBm with a peak system efficiency (SE) of 40.6%. When transmitting a 1.4 MHz, 64 QAM LTE signal it outputs 18.8 dBm at 21.6% SE, with a measured EVM of 2.65 %-rms at 1.8 GHz.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114375500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Varga, Fabian Speicher, A. Ashok, I. Subbiah, M. Schrey, R. Wunderlich, S. Heinen
{"title":"Improving the linearity of wideband receiver systems by component IM3 phasor manipulation","authors":"G. Varga, Fabian Speicher, A. Ashok, I. Subbiah, M. Schrey, R. Wunderlich, S. Heinen","doi":"10.1109/RFIC.2017.7969004","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969004","url":null,"abstract":"A linearity improvement technique for receiver systems is presented and verified on a 130nm CMOS high-IF upconverter with 470 –790MHz input and 2.4–2.6 GHz output frequency range, enabling WLAN and LTE transceivers to be used as TV White Space Devices. The upconverter reaches a stable IIP3 of 15 dBm, NF of 8 dB and Gain of 7 dB. A linearized LNA and mixer are used as a composite architecture to combine low NF with, even though, high IIP3. Instead of further maximizing the linearity of the components, the overall performance is optimized on the system level by manipulation and complementary exploitation of the remaining third order intermodulation products of the components.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Buckel, T. Mayer, T. Bauernfeind, S. Tertinek, C. Wicpalek, A. Springer, R. Weigel, T. Ussmueller
{"title":"A highly reconfigurable RF-DPLL phase modulator for polar transmitters in multi-band/multi-standard cellular RFICs","authors":"T. Buckel, T. Mayer, T. Bauernfeind, S. Tertinek, C. Wicpalek, A. Springer, R. Weigel, T. Ussmueller","doi":"10.1109/RFIC.2017.7969028","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969028","url":null,"abstract":"A multirate, fractional-N RF digital phase-locked loop (DPLL) phase modulator implementation for polar transmitter supporting cellular communication standards up to 4G LTE-A is demonstrated for the first time. The RF-DPLL integrates LC-tank-based digital-controlled oscillator (DCO) cores with ΔΣ-noise shaping and fractional sample rate conversion to account for a broad range of frequency bands and spectral emission requirements. A two-point modulation with different sampling rates and signal scaling is applied to optimize the system for operation in narrow-band and wide-band phase modulation. DCO predistortion and DCO gain estimation is implemented to achieve sufficiently low in-band distortion. Measurement results of the RF-DPLL system as part of a polar transmitter implemented in 28-nm CMOS are shown, fulfilling 3GPP specifications for LTE-A uplink.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"307 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116594202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fully integrated CMOS X-Band power amplifier quad with current reuse and dynamic digital feedback (DDF) capabilities","authors":"F. Bohn, Behrooz Abiri, A. Hajimiri","doi":"10.1109/RFIC.2017.7969054","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969054","url":null,"abstract":"A 10GHz fully-integrated stacked PA quad with dynamic digital feedback and control loops provides total output power of 200mW at 37% PAE. It utilizes data provided by multiple on-chip sensors to maintain safe operating conditions and regulate the individual power PA power supply voltages and independent power control for each PA. This digitally controlled stacked PA quad with on-chip matching allows higher operation voltages while maintaining current consumption constant, leading to higher overall system efficiency, as ohmic drop losses under large supply-to-breakdown voltage ratios are reduced.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"540 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131848446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gengzhen Qi, B. van Liempd, Pui-in Mak, R. Martins, J. Craninckx
{"title":"A 0.7 to 1 GHz switched-LC N-Path LNA resilient to FDD-LTE self-interference at ≥40 MHz offset","authors":"Gengzhen Qi, B. van Liempd, Pui-in Mak, R. Martins, J. Craninckx","doi":"10.1109/RFIC.2017.7969071","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969071","url":null,"abstract":"This paper proposes a self-interference-resilient LNA for the FDD-LTE covering 0.7 to 1GHz. It incorporates a switched-LC N-path network with gain-boosting and optimum-biasing techniques to enhance the out-of-band (OOB) linearity at ≥40MHz offset. Implemented in 0.18µm SOI CMOS, the LNA achieves >31.2dB output rejection, +26.2dBm (+8dBm) OOB-IIP3 (iB1dB) at ≥40MHz offset and 6.8dB blocker NF at +4dBm blocker power for the default mode, while consuming a reasonable power of 48.4 to 62.5mW. When reconfigured to high-rejection mode, the LNA offers a tunable cancellation notch improving the output rejection to >50dBc.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"476 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115315761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Broadband effect of linear tapered transitions between probe pads and GCPW signal lines on-chip","authors":"T. Stander","doi":"10.1109/RFIC.2017.7969036","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969036","url":null,"abstract":"To effect a low-reflection interconnect between GSG probe pads and on-chip GCPW, a linear taper between the signal pad and the GCPW signal line is often included. This work evaluates, both in parametric simulation and experimentation, the effect of this taper shape to the input reflection in the band 1 – 110 GHz. It is found that, although longer tapers offer some advantage below 30 GHz, the taper ultimately impedes the input reflection of the interconnect.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124715162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}